Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5-7 years of experience in SOC Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Overview Qualcomm WLAN HW team in Bangalore is responsible for developing and delivering best in class WLAN/WiFi solutions which are setting benchmark in wireless industry. In this role of WLAN Verification Engineer, you will be verifying the PHY Sub-System from both TX and RX perspective. The responsibilities will majorly include : Understanding of WLAN PHY TX and RX design paths, Algorithms that control the various aspects of wireless systems Develop test plan to verify WiFi Standards including 11BE, sequences and design components. Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches Successful candidate will be required to collaborate with worldwide design, silicon, and architecture teams to achieve all project goals. Hence, we are looking for candidates with strong communication skills . 3+ years industry experience with below skillset : Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology Experience in formal / static verification methodologies will be a plus Good understanding of WiFi Standards is a plus Experience with GLS, and scripting languages such as Perl, Python is a plus Education Requirements BE/BTech/ME/MTech/MS Communication Engineering and/or Electronics, VLSI from reputed university preferably with distinction Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must . Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must . Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required . Hands on experience in Multi Clock designs, Asynchronous interface is a must . Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

About The Role : About The Role :: Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. If you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. This job opportunity is in Client Windows system integration & validation team which provides scope to work in a fast paced, leading edge environment with endless possibilities of innovating and learning across Display, Media & 3D domain E2E use-case validation & debug. We strive to lead the industry through continuous innovation and world-class engineering. This is an excellent opportunity to pursue your dream job. As a Graphics Validation Engineer, you will define, develop, and perform platform validation of E2E Graphics usages, focusing on media, display and 3D system level features on Windows. Review functional requirements for test case creation and validation methodologies. Develop & apply various software tools and techniques to ensure validation coverage goals are met as per the specifications. Execute validation plans flawlessly to meet the quality goals. Perform system level debug of failures to identify root causes and collaborate with IP teams for issue fix/resolution. Work with architecture, IP and board teams to maintain and improve validation strategy, debug methodologies for E2E graphics usages and to meet desired product specifications. Job Responsibilities include (but not limited to): Define & develop system level validation plans and strategies to integrate & validate Windows platform Graphics (display, media, 3D) use-cases as per the requirements Work closely with other teams in Architecture, BIOS, Gfx driver, hardware, Firmware & board team to ensure readiness of Graphics use-cases for validation purpose Validate and debug software across the stack for a specific product, platform, windows based Graphics features, or technology Issue triage/debug and faster resolution by collaborating with cross functional IP, Hardware, Firmware, OS and BIOS teams Analyze the results to ensure correct functionality, triages failures, and recommend or develop corrective actions Support Quality events by proactive coordination with relevant stakeholders Effectively collaborate and communicate with global stakeholders Publish Graphics reports summarizing validation results to the relevant teams Assess the state of the art and employ new methods to improve debug, quality Identify opportunities to automate test cases and develop software automation test scripts and utilities Qualifications Job Qualification Candidate should hold BTech/MTech in computer Science or Electronic streams with excellent hold on key engineering subjects Candidate should have 5+ years of relevant experience Strong self-initiative and persistence with ability to deal with ambiguity to focus and achieve end goals. The candidate must have a high focus on discipline in execution, a relentless pursuit of quality and excellent customer orientation. Good debugging and problem-solving skills, comfortable with the use of software and platform tools to diagnose and debug platform Graphics issues Good understanding of Windows Graphics domains namely media, 3D, Display Technologies & E2E platform test case creation and validation. Good knowledge of programming languages like C/C++ or scripting language like Python Must have experience in Window Graphics driver Architecture and its interaction with platform level components Must have excellent written and oral communication skills and be able to effectively collaborate and communicate with global stakeholders. Experience and hands on skills with WinDBG, ITP, Logic Analyzers. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role : You will be part of world class Intel Emulation Solutions team (ES) team responsible for driving the Emulation strategy across Intel's next generation products. ES team is leading the innovations and new technologies with Virtual Platform/Emulation/Hybrid solutions partnering with Intel teams as well external EDA vendors accelerating Intel product TTM. In this role you will be responsible for defining and developing new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation model usability for preSilicon and postSilicon functional validation as well as SW development/validation. You will also develop improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. You will interface with and provide guidance to preSilicon Validation teams for optimizing preSilicon validation environments, test suites and methodologies for emulation efficiency. You will be responsible for developing and applying automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. Qualifications Must have a Bachelor's degree or Master's degree in Electrical, Electronics or Computer Engineering with relevant experience of at least 3+ years Experience with emulators such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce for large scale designs Strong understanding of Computer architecture, design principles, validation methodologies and tools Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog based verification techniques. Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environments. Experience in SW Programming/scripting and debug such as assembly, C, C++, Perl, Python Prior expertise in CPU, Coherency, reset, Global Flows, Power management, memory, PCIe highly desirable Prior experience in System Validation is a plus. Must possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow s future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. We are seeking an experienced ASIC Verification Manager/Lead to lead the verification efforts for ARM multi core advanced CPUs based designs. The ideal candidate will have a strong background in RTL verification methodologies, UVM, C and SystemVerilog, along with proven leadership skills in managing and technically guiding verification teams. You will be responsible for driving pre-silicon verification, collaborating with cross-functional teams, and ensuring the successful validation of high-performance SoCs. Why Join Us Opportunity to work on cutting-edge ARM-based SoC designs. Lead a team in a high-impact, fast-paced environment. Competitive compensation and career growth opportunities. Work alongside some of the best minds in the semiconductor industry. What Youll Do Lead and manage the ASIC verification team to ensure high-quality verification of ARM Advance CPU based SoC designs. Define and implement verification strategies, test plans, and methodologies, release flows for complex IP and SoC design. Develop and maintain UVM-based and C-based testbenches, including constrained random testing, functional coverage, and assertions. Drive pre-silicon verification and support emulation, and FPGA prototyping. Collaborate closely with design, architecture, software, and post-silicon validation teams to ensure comprehensive verification coverage. Analyze and debug simulation failures, regressions, and coverage gaps to ensure complete verification closure. Drive automated verification infrastructure to improve efficiency and reliability. Mentor and guide junior engineers, fostering a culture of innovation and technical excellence. Track project milestones, verification progress, and report status to stakeholders. What Youll Need Bachelor s/Master s degree in Electrical Engineering, Computer Engineering, or a related field. 15+ years of experience in ASIC/SoC verification, with at least 3+ years in a managerial and leadership role. Expertise in ARM architecture, AMBA protocols (AXI, AHB, APB), and memory subsystems, PCIe, D2D Technologies. Strong hands-on experience with UVM, SystemVerilog, and functional verification methodologies. Experience with Excelium, VCS, Questa, or other industry-standard simulators. Familiarity with Formal Verification, Gate level Simulations, Static Timing Analysis, and UPF based Power-aware Verification. Hands-on experience in C/C++, Python, or Perl scripting for automation. Experience with Emulation, FPGA prototyping, and hardware-software co-verification is a plus. Excellent leadership, communication, and problem-solving skills. Preferred Qualifications: Experience in high-performance computing (HPC) or data center SoC verification. Knowledge of Arm architecture, Security verification, and Cache coherency protocols. Familiarity with post-silicon validation and bring-up processes. Prior experience working in tapeout-focused environments. We have a flexible work environment to support and help employees thrive in personal and professional capacities. As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow s future by accelerating the critical data communication at the heart of our digital world - from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What Youll Do Will be responsible for verification of IP, Block, or Subsystem at Soc Level Generate appropriate documentation for verification Responsible for analyzing/debugging given blocks/tasks in verification Should be able to develop and own the verification environment, verification components developed You will report to Lead Engineer What Youll Need: 5+ years of experience with a Bachelors/ masters degree in the field of Electrical, Electronics, or computer engineering Should have a good understanding of verification flow, challenges, and requirements of functional verification Have worked on IP level or Block level or SoC level functional verification Experience with digital verification aspects such as constrained random verification, functional coverage, code coverage, assertions, methodology philosophy Expert in System Verilog, Verilog, and OVM/UVM verification methodology Have working experience on AMBA interface protocols (AXI, AHB, APB) Knowledge of Verilog/System Verilog, digital simulation, and debugging is a must Hands-on experience on working one or more of the following protocols is a must - UART, I2C, SPI, QSPI, I3C, eMMC, CAN, Hands-on experience working with one or more of the following protocols is desired - PCIe, USB, DDR, LPDDR, GBE, SATA Experience with Perl, Python or similar scripting languages will be helpful Ability to adapt learn, quickly and willingness to proactively take on responsibilities beyond the job description to accomplish team goals. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Great compensation package Restricted Stock Units (RSUs) Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

SystemC requirement with 2-10 years of experience in our team and looking for profiles Note, please apply only with the following skills SystemC experience (preferred). Firmware experience with decent C++ expertise and SoC knowledge. ESSENTIAL DUTIES AND RESPONSIBILITIES: Development of C++/SystemC models for complex ASIC IPs, SOCs and Flash Memories. Create System Level Tests and/or Standalone Unit Tests and verify the models. Keen on schedule and quality of the deliverables. Timely support to the stakeholders enabling software bring-up. QUALIFICATIONS: B.E/B.Tech or M.E/M.Tech in Electronics, Computer Science or related streams. 2 - 10 years of relevant experience. REQUIRED SKILLS: Proficient in SystemC/TLM, C++, C. Hands-on experience in development of functional/approximately timed models using SystemC/C++. Hands-on experience in embedded system test development using C. Proven ability to troubleshoot and analyze complex problems. Excellent grasp of Digital Fundamentals. Ability to multi-task and meet deadlines. Should be a Fast learner and a team player. Good written and verbal communication skills. PREFERRED SKILLS: Understanding of Computer Architecture, SoC, CPU (ARC/ARM/RISC-V/etc,), Bus Architectures, RTOS. Exposure to scripting languages like Python. Experience with Visual Studio programming environment Working Knowledge of Interface Protocols like PCIe, AXI, USB, UFS, NVMe, SD

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology. InnoPhase Inc., DBA GreenWave Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products. Job Description As Technical Lead – Design Verification, you will be the key contributor of ORAN SoC product design verification team and collaborate with FW & design team for product requirement definition, micro architecture study. You will participate in the verification of novel ORAN SoC functional blocks for high-performance applications such as LTE and sub-6 GHz 5G cellular base stations. Beyond the technical contribution, you will also interface with functional leads in project coordination for schedule tracking on deliverables and dependencies. You also will provide technical advice to young engineers to ensure the quality of work. This role is an excellent opportunity for engineers with 10+ years of industrial experience to grow their technical career as well as leadership to climb up corporate ladders and join the exciting cellular product market space. Key Responsibilities Develop testbench environment to perform verification of the design at IP/ Subsystem and SoC Level using SystemVerilog and UVM. Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs. Develop and execute verification plans based on design specifications and collaboration with architects and designers. Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases. Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification. Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. Assist in emulation, FPGA, prototyping efforts. Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts. Job Requirements Master's and/or Bachelor’s degree in engineering (or equivalent) in EC/ EE/ CS. 10 or more years of experience in design verification with proven experience in full chip verification from test plan development to tape-out sign-off. Good understanding of the complete verification life cycle (test plan, testbench through coverage closure). Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from the scratch. Proficient in SystemVerilog, Verilog/VHDL, UVM and C; and scripting languages like Python, Perl and Tcl/Shell. Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based test bench environments, writing SystemVerilog Assertions (SVAs), with embedded software design and testing. Strong knowledge about multiple testbench architectures, industry-standard interfaces/ protocols (AXI, AHB, APB, , PCIe, PIPE interface, Serdes, UART, SPI, I2C, QSPI, DMA etc). Experience in Cadence Design Tools/ Environments and exposure to Cadence VIPs/ UVCs is plus. Track record of successfully executing block or chip-level verification plans. Excellent communication and presentation skills, energetic and self-motivated. Work effectively with an off-site/ offshore design and verification teams across locations. Benefits Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick & parental leaves.

Looking for PCB layout design Engineer with the following requirements: Hands-on experience in complex, high-density, high-speed PCBs, Analog, Digital, RF, mixed-signal PCB layout design. Exposure with complex 2U, 3U server form factor-based PCB designs. Hands-on experience with High-speed interfaces like DDR3,DDR4/5, LPDDR, , PROCESSORS, FPGA, PCIE, USB, SATA, MIL-1553, ADC, DAC, ETHERNET, NAND & NOR FLASH, SD, RS-422, BLUETOOTH 4.0, WIFI, GPS, GSM etc. Hands on Complex layout HDI designs with multiple BGAs and Multiple Fine pitch BGA (0.8mm and 0.5mm) of high pin count (2084 pins). Library creation as per IPC 7351 standard. Electrical Constraints setup for high-speed modules to match its requirement (Length match, impedance, delay tuning requirements) Experience in Power supply layout design types: AC to DC, DC to DC converters and SMPS. Creation of file type conversions from PCB to DXF, IDF, Step file collaboration with Mechanical Engineer. Power supply layout designs & its critical requirements to meet stringent isolations. Gerber validation and generations of final deliverables for DFM. Working experience on Gerber viewers using Cam350, ODB++ viewer. Collaborating with multiple functional teams like design, SI/PI, mechanical, DFM, DFA etc. in a product development environment knowledge on Power dc, Thermal design, simulation and analysis knowledge of OrCAD schematic Design Tool Collaboration with cross functional teams: Software, Electrical, Mechanical and PCB CAD teams Hands-on experience with Cadence Allegro/Altium EDA/PADS tools is essential. Education Requirements: B. Tech/B.E./M. Tech./M.E. Shift: 9:30 AM to 6:30 PM Work Mode: Office (Monday to Friday)

Overview UVM Based verificaton at SOC level Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bachelors/ Masters degree or higher in EEE/ECE 5+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

As a senior member of the Android Wi-Fi team, you will be responsible for implementing new Wi-Fi features and standards (Wi-Fi 6/6E/7) that can span across different layers of Android (apps/framework/HAL), Wi-Fi Driver and Wi-Fi Firmware. You will be responsible for debugging connection, low-power and other performance related issues. You will be responsible for keeping track of all changes the Google does to Android Wi-Fi stack and implementing support for different Infineon chips. Responsible for keeping track of supplicant/ hostapd changes in the open-source community and planning those support for Infineon Wi-Fi Chips and upstreaming those patches to open source and Google repos. You are also responsible for ramping up on other skillsets like RTOS, Firmware and Linux Drivers. Job Description In your new role you will: Will be responsible for bring up of Android on different H/W platforms which will include debugging at driver, Linux Kernel, SDIO/PCIe bus driver and android Wi-fi stack layers. Will be responsible for developing new Wi-Fi features that could span across android stack, Wi-Fi driver and firmware and should be able to debug Wi-Fi driver and firmware level issues. Will be responsible for understanding the changes done by Google to Wi-Fi architecture for new android versions at different layers: APPs, framework, HAL, supplicant, hostapd, driver and implement those support for Infineon Driver and Firmware. Should have good knowledge and able to debug issues at all layers of Android Wi-Fi Stack including Drivers. Should have good understanding of the Android CTS/VTS flow and be able to debug issues and add new test cases. Will be responsible for debugging Wi-Fi Throughput issues by analysing air sniffer and Wi-Fi Driver and kernel logs. Responsible for fixing Wi-Fi issues at Android, Wi-Fi Driver and Firmware level. Should have good understanding of Android Connectivity Manager and IP Stack and be able to debug networking issues. Will be responsible for upgrading Android Supplicant and Hostapd versions to latest versions from community. Your Profile You are best equipped for this task if you have: 12+ years experience working on Android Platform . Knowledge of 802.11 and good communication skills. Good networking knowledge of TCP/IP . Candidate should be good in multitasking of assignments and work according to defined priorities. Hands on with bringup of Android on AOSP supported platforms (VIM3 /IMX8/ HIKEY..) Strong working knowledge on Android Framework mainly Wi-Fi interfaces from Settings APK to HAL and Driver layers. Sound knowledge of Linux device driver development. Specially network device driver is plus with respect to how TCP/IP stack would interact with driver under various OSs. Understanding of HIDL, AIDL and CTS / aCTS test and development Frameworks Good to have understanding of "C" and "C++" programming and good at RTOS Concepts, very strong understanding of system primitive. Ability to identify issues in the driver synchronization between different threads, also between interaction of application. Strong working knowledge of interrupt handling in the device driver. Ability to identify bottle neck in the driver performance. Strong knowledge of internal working of one of the embedded OS Linux, Android. Have good hands-on for Android 12/13 and 14 OS or Android Auto system and Mobile framework

Knowledge & experience of Microarchitecture, RTL, Synthesis, STA and CDC. Job Description In your new role you will: Defining, designing, and implementing very complex logic blocks. Performing architecture analysis and feasibility for these complex blocks. Working with the SoC lead for full chip implementation from launch to production . Performing RTL design, synthesis and DFT strategy, clocking strategy, validation and verification support. Utilizing industry standards and proprietary tools and methodologies for design, chip integration and design for test. Supporting cross functional teams, including product and test engineering, chip integration, circuit design, verification and validation, in taking SoC into production. Participating in customer design reviews Participate in detailed planning and monitoring to deliver on time milestones. Mentor and develop junior engineers. Your Profile You are best equipped for this task if you have: Education and experience required BS + 12-13 years experience, MS + 10-11 years experience Knowledge & experience of Microarchitecture, RTL, Synthesis, STA and CDC. Experience with Logic Synthesis, Low power, Equivalence, Linting, CDC and DFT tools. Strong written and verbal communication skills are required. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.. Expertise in dealing and designing with complex IPs from different sources onto the same piece of silicon. Expertise in USB / PCIe / micro-controller / USBPD / Power Controller space is an added advantage

We are seeking a PCIe device developer with expertise in PCIe driver and Linux kernel development. The ideal candidate will work on our DPU and AINIC firmware - low-level system software, enabling hardware functionality, optimizing performance, and ensuring seamless integration between hardware and software layers. Key Responsibilities: - Develop PCIe driver/features for our AINIC and DPU product line - Optimize PCIe driver performance, including power management and low-latency data transfers - Work with kernel-level programming in Linux including experience with sysfs, procfs, and PCIe Subsystem - Debug and troubleshoot PCIe bus communication, DMA, interrupts, and memory mapping issues - Provide support for hot-plug and interrupt mechanisms - Collaborate with hardware team to understand PCIe components like serdes and bringup in software Required Skills & Experience: 10-15 years of experience in managing PCIe devices, Linux kernel programming, device driver development, and system software engineering. Proficiency in C programming for system-level software. Good understanding of PCIe enumeration, link training, device initialization sequence, configuration space handling, SR-IOV, bare-metal and hypervisor VM architectures Strong debugging and troubleshooting skills using kernel logs, GDB and other debugging tools. Experience in hardware bringup, bootloaders, and ARM architecture. Familiarity with Buildroot, or other embedded Linux systems. Knowledge of memory management, interrupts, and scheduling in Linux. Educational Qualifications: Bachelor s or Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field.

We are seeking an experienced Director of Product Test Hardware Engineering to lead and drive the development and deployment of cutting-edge test and validation hardware solutions. The role focuses on advanced Automated Test Systems (or ATE) for production test, characterization, and validation applications, emphasizing high-speed interface testing, high-parallelism capabilities, and stress board design. This position requires a strategic thinker with hands-on expertise to ensure optimal hardware performance, test coverage, and manufacturability in a fast-paced, innovative environment for Automotive Microcontrollers. Job Description In your new role you will: Leading a team of 10+ engineers from diverse background with strong technical knowhow. Ensure FTR (First Time Right) delivery in a time-boxed approach. Develop and execute the roadmap for validation and test hardware solutions aligned with organizational goals for high power, speed and parallelism requirements. Collaborate with cross-functional teams, including product engineering, software, and validation teams, to meet product test goals. Influence the definition of configurations of next generation testers or validation environment. Innovation of new tools, methodologies, workflows and ideas to continuously improve Validation and Test Hardware design efficiency. Responsible for R&D Budget of ~5+Mio EUR across multi platforms and products. Oversee the design, development, and deployment of advanced hardware solutions, including ATE load boards, probe cards, and validation/stress boards. Ensure robust designs that meet high-speed signal integrity, high-power delivery, and manufacturability requirements. Ensure and propose the most optimized parallelism of Production Test. Hardware to project to best benefit the overall project financial landscape, by considering the CoT (Cost of Test) and TT (Test Time) impact Define and own the process and workflow of Validation / Production Test hardware Specification, Implementation, Verification and Test Cell Definition. Lead initiatives for production test, characterization, and validation hardware to support high-speed interfaces and high-parallelism devices. Manage the development of hardware solutions for functional and parametric testing across all lifecycle stages, including NPI and volume production. Establish best practices for testing high-speed interfaces, ensuring compliance with industry standards and minimal signal degradation. Drive high-parallelism testing to maximize throughput and efficiency in high-volume production environments. Build and mentor a team of test / validation hardware engineers, fostering innovation and excellence. Set performance goals, manage deliverables, and support professional growth within the team. Support growth of team competencies for next level of complexity of products. Act as the primary interface between hardware engineering teams and external stakeholders, including customers, suppliers, and contract manufacturers. Provide technical expertise and support for customer escalations and quality concerns. Your Profile You are best equipped for this task if you have: Bachelor s or Master s degree in Electrical Engineering or a related field. 12+ years of experience in semiconductor validation and test engineering. Proven expertise in Advantest (V93k) or similar ATE platforms. Strong background in high-speed interface testing (e.g., PCIe, DDR, GETH, HSPHY). Experience with high-parallelism test methodologies for high-volume production. Familiarity with stress board design for reliability and environmental testing. Solid understanding of signal integrity, power integrity, and thermal management principles. Strong knowledge of PCB design tools (e.g., Cadence Allegro, Mentor Graphics). Excellent analytical and problem-solving skills with a data-driven approach. Leadership skills with a track record of managing multidisciplinary and multi-cultural teams. Effective communication and stakeholder management abilities. Openness to new ideas and changes based on new dynamics. Candidates with consumer application background will also be considered.

Design, develop, and maintain x86 BIOS/UEFI firmware, ensuring robust and efficient solutions aligned with project specifications. Collaborate with hardware and software teams to support x86 CPU/APU architectures, optimizing performance through expert-level C programming. Work on UEFI bootloaders and applications, focusing on UEFI-based storage protocols such as AHCI, SATA, and NVMe. Perform platform hardware analysis and interpret processor specifications to support coreboot mainboard porting and integration. Integrate and customize BIOS code bases (AMI, Insyde, or Phoenix BIOS) to meet customer and platform requirements. Debug and resolve firmware-related issues, leveraging deep knowledge of UEFI framework concepts and storage protocols. Contribute to the development of Android UEFI-based bootloaders for x86 platforms, if applicable. Maintain code quality through rigorous testing, documentation, and adherence to best coding practices. Provide technical guidance and mentorship to junior developers, supporting knowledge sharing and team growth. Collaborate with cross-functional teams to ensure smooth firmware delivery, addressing technical challenges proactively. Skills Must have 5-15 years of experience in the x86 BIOS/UEFI development Experience with x86 CPU/APU architectures and associated compilation tools Expert in C language Familiar with at least one BIOS code base (AMI, Insyde, or Phoenix BIOS) Experience working on UEFI bootloader or UEFI applications mainly involved in UEFI-based storage protocols AHCI, SATA, and NVMe. Will be good if have any experience in Android UEFI-based Bootloader for x86. Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required. Good understanding of UEFI framework concepts and Storage protocols. Nice to have Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. Good understanding of industry-standard protocols like SATA, NVMe, AHCI, PCIe, SPI, eSPI etc. Good understanding of specifications like ACPI, SMM. Good understanding of x86-64 architecture from BIOS developers perspective. Good understanding of UEFI BIOS Boot flow. Bachelors degree in computer science engineering from a reputed college Masters degree from a reputed university is a big plus

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Principal Design Engineer Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job responsibilities: Experience level: 10-15 years Education: BE/ B Tech/ ME/ M Tech / MS In-depth understanding of high-speed Serdes/Memory interface circuits like I/O s, PLL s, Clocking, Datapath s. Hands on experience on PCIe Gen3/4/5/6, GDDRx/DDRx/LPDDRx memory interface circuits. Strong Analog Design and I/O Design fundamentals. Knowledge of ESD/Reliability/SI/PI. Experience in leading complex IP s , managing cross functional dependencies needed. Experience in leading and mentoring Junior Engineers. Must have excellent written and verbal communication skills as well as good problem-solving skills. Prior experience of working on cutting edge technology nodes like 16nm/10nm/12nm/7nm is added advantage. We re doing work that matters. Help us solve what others can t.

About Client Hiring for One of the Most Prestigious Multinational Corporations! Job Description Job Title : Hardware Engineer Required skills and qualifications: Must knowledge on Design and Development of power supply section (PMIC, LDO, BUCK, BOOST, Buck-Boost, Protection circuits). High speed circuit design (PCIe, USB, Ethernet, RGMII, MIPI CSI, DSI, SGMII, FPDLink, HDBT), Hardware Circuit Simulations, Hardware validation, PCB design & Verification in Automotive domain projects. Knowledge on Analog circuit, Mixed Signal, Microcontrollers, Microprocessor and SOC. High Speed circuit design, experienced on Mentor Graphics Xpedition, DxDesigner, Pads Layout, Altium Expertise in BOM preparation, document preparation using MS office excel, word, Visio, Planner and presentation. Having good knowledge in Pre-compliance test (EMI, EMC, ESD) Qualification : Any Graduate or Above Relevant Experience : 8 to 12 yrs Location : Bangalore/Pune CTC Range : 25 to 30 LPA Notice period : 0 to 60 days Mode of Interview : Virtual Mode of Work : In Office Sana F Staffing analyst - IT recruiter Black and White Business solutions PVT Ltd Bangalore, Karnataka, INDIA sana.f@blackwhite.in I www.blackwhite.in +91 9902578775

Grounds up verification environment development using SV/ UVM is a must5+ yrs Bangalore/ Pune One of the Serdes of high speed protocols like PCIe or USB 3 or MIPI Testplanning, AMS Setup, Experience in wreal, RNM, Verilog A VCS Primesim AMS and Primesim XA tool lExperience in wreal, RNM, Verilog A, exp in System Verilog and UVM

Execute any internal project or small tasks of customer project in any field of VLSI Frontend Backend or Analog design under minimal supervison from the Lead Outcomes: As an Individual contributor work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Analyse and complete the assigned task in the defined domain(s) successfully on-time with minimal support from senior engineers Ensure quality delivery as approved by the senior engineer or project lead Measures of Outcomes: Quality -verified using relevant metrics by Lead/Manager Timely delivery - verified using relevant metrics by Lead/Manager Reduction in cycle time and cost using innovative approaches Number of trainings attended Outputs Expected: Quality of the deliverables: Clean delivery of the module in-terms of ease in integration at the top level Ensure functional spec / design guidelines are met 100% of the time without deviation or limitation Documentation of the tasks and work performed Timely delivery: Meet project timelines as given by the team lead/program manager Help with intermediate tasks delivery by other team members to ensure progress Teamwork: Teamwork participation; supporting team members in the time of need Able to perform additional tasks in case of any team member(s) is not available Innovation Creativity: Pro-actively plan approach towards repeated work by automating tasks to save design cycle time Participation in technical discussion training forum Skill Examples: Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one) EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Understands IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Knows Bus Protocol AHB / AXI / PCIe / USB / Ethernet / SPI / I2C Microprocessor architecturec. Good knowledge of Physical Design / Circuit Design / Analog Layout d. Good understanding of Synthesis DFT Floorplan Clocks PR STA Extraction Physical Verificatione. Knowledge in Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Required technical skills and prior design knowledge to execute assigned tasks Ability to learn new skills in case required technical skills are not present to a level needed to execute the project Able to deliver tasks with quality and 100% on-time per quality guidelines and GANTT Strong communication skills Good analytical reasoning and problem-solving skills with attention to detail Knowledge Examples: Previous project experience in any of the design by executing any one of the following RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Good Understanding of the design flow and methodologies used in designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager per skill set Required Primary Key skills - STA, nano time You will be part of a Physical Design / Timing Closure team for projects with GHz freq range and cutting-edge technologies. You will develop timing constraints for full chip or block level and be responsible for STA signoff for a complex multi-clock, multi-voltage SoCs. You will be responsible for Synthesis, Timing Analysis (STA), CTS at Full Chip or block level for Lower tech node ( Below 14nm) Desired Skills and Experience: B. Tech. / M. Tech. with 2-8 years of experience in Synthesis, STA Expertise in synthesis of complex SoCs at block/top level and writing timing constraints for complex designs with multiple clocks and multiple voltage domains Worked on pre and post layout timing analysis and resolving the issues Expertise on post layout timing closure for multiple tape outs, including timing ECOs and STA signoff Expertise in I/O constraints developments for Industry standard protocols (e.g. DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display etc...) Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm, 10nmGood knowledge of EDA tools from RC, DC, PT, PTSI Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints Good knowledge of VLSI process and device characteristics Good understanding of deep submicron parasitic effects, crosstalk effects etc.TCL, perl scripting

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills Experience in Hifi Processor, Soundwire interface, ANC, DMA, I2S verification experience is a Plus. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12-15 years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Verification & Validation team is currently looking for self-motivated engineers who will perform ARM or DSP based SOC Pre-Si and Post Si validation including system level validation and debug. The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Experience in SoC pre/post silicon validation. ARM based System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug. Perform system level validation and debug Debug experience with Lauterbach Trace32 environment. Test equipment like Logic analyzer, Oscilloscope and Protocol analyzers. Embedded software development of low level hardware drivers in C language. Working experience related to one or more of the following is required. ARM/DSP Processors/USB/PCIE, Ethernet Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-6yrs experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. What we are looking for : Minimum Qualifications: 2-7 years (with Btech) or 5 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing. Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet. Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers. Preferred Qualifications: Experience in PCIe/UCIe LTSSM states is a plus. 1-2 years of experience in FPGA Design and Schematic design is a plus. 1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus. Familiarity with Verilog RTL coding for FPGA, python, C/C++ Good communication skills Candidates are expected to be passionate about analog and digital electronic circuit design. We re doing work that matters. Help us solve what others can t.

Role : Silicon Validation Experience: 4+ years Location: Bangalore Must to have skill Silicon Validation Test Automation-Python FPGA emulator environment Good to have skill Domain: PCIe, SerDes, Serial interfaces - UART, SPI, I2C About the client: It is an Indian multinational corporation that provides information technology, consultant and business process services. It is one of the leading Big Tech companies