We are seeking a skilled Analog Layout Engineer to join our team at Nsemi. In this role, you ll be responsible for designing and optimizing analog and mixed-signal IC layouts, ensuring high performance and reliability. Your expertise will involve layout creation, verification, and adherence to design rules and specifications. Ideal candidates will have strong experience with analog circuit design, proficient use of layout tools, and a keen eye for detail. Join us to work on cutting-edge projects and contribute to the advancement of semiconductor technology. Qualification Required: Typically requires minimum of 3+ years of experience in Analog Circuit Design Bachelors / Master Degree in E&E and E&C Strong communication & team work skills Roles And Responsibilities: Expert in Power Management including hands-on DC-DC Converter, other precision analog circuits like operational amplifiers, Band-gap references, POR, Current Limit circuits, LDO regulators, comparators, oscillators etc. Experience in transceiver design for high speed interface such as Serdes, highspeed,DDR, HBM, PCIe, USB3, JESD204, Experience in transceiver design for high speed interface such as PLL,CTLE, DFE, CDR,PCIe, USB3, JESD204 Candidate should have taken atleast one block from circuit design and should be guide layout engineers for closure. Strong competency in small signal analysis and various frequency compensation techniques. Understanding of chip level ESD/LU requirements. Top-level integration, Block-level verification across PVT, Statistical Mismatch & mixed signal Verification. Hands-on working with Tools - Virtuoso/Tanner for schematic/model design & verification. Work closely with the Layout engineer to get optimized IP layout. This involves managing IP planning. Experience with Silicon validation and debug process. Planning, managing full-chip execution with team. Advantage if candidate has experience with high-current designs and/or multi-phase operation switching regulators

The CCS Groups Firmware (FW) team in Pune is dedicated to developing cutting-edge products with a strong focus on the data center domain. As part of a larger global firmware development organization, the Pune team plays a key role in advancing firmware technologies. As a Senior Staff Manager - Firmware , you will lead a growing team responsible for developing end-to-end firmware solutions for some of our most advanced technologies. This role requires strong leadership and technical expertise to drive firmware development in alignment with Marvell s product roadmap. Lead and mentor a high-performing firmware development team. Collaborate with Architecture and Customer Support teams to translate market and customer needs into product requirements. Plan, manage, and execute release schedules, ensuring timely delivery of high-quality firmware. Drive product definition and requirement changes, effectively managing schedule, feature, and cost trade-offs . Oversee direct and matrix management of firmware engineers. Maintain frequent communication with customers to drive optimal firmware development. Plan, present, and track firmware development schedules to ensure seamless execution. Manage capital equipment purchases, lab space forecasting, and budget planning . Hire, retain, and develop top firmware talent while fostering a culture of continuous learning. Work closely with Firmware Simulation, Firmware Validation, SoC, System Architecture, and cross-functional teams to ensure product success. Collaborate with teams across global locations within and outside of Marvell . This role requires a strategic mindset, strong leadership skills, and deep technical expertise to drive innovation and execution in firmware development. What Were Looking For Education: BE/B.Tech/BSc or ME/M.Tech/MSc in Electrical Engineering, Computer Engineering, or a related field. Technical Expertise: Strong background in software/firmware engineering. 15+ years of experience in software design, development, and testing. Experience developing firmware for PCIe storage products. Proficiency in C, C++, Python, and embedded firmware tools/techniques. Knowledge of NVMe, PCIe, Security, and TCG/Opal. Familiarity with processor architectures, such as ARM. Leadership & Project Management: 5+ years of experience leading and managing software/firmware teams. Strong technical project management skills, including scheduling, risk assessment, and execution. Expertise in tracking and management tools, with the ability to work in a fast-paced, agile environment. Communication & Collaboration: Strong written and verbal communication skills in English, with the ability to provide regular updates to execution teams and key customers. Proven ability to collaborate across teams, including System Architecture, SoC Design, and Marketing. Ability to work effectively in a dynamic and fast-paced environment.

- Must have hands on designed/implemented/Integrated DDR controller or DDR Phy design for a project(ASIC or FPGA). - Should be excellent in DDR protocol knowledge. - Must be an expert in micro architecture and RTL coding. Skill set needed - Verilog, SoC & Sub-system RTL Integration, knowledge of industry known standards Interfaces (AXI, AMBA, NOC, Fabric, UCIE, PCIE, SATA, DDR etc. etc.) Scripting : (Shell, python, ruby, perl etc.), CDC & LINT Checkers, Synthesis, LEC, Constraints/SDC understanding, Clocking, UPF, Register roll up. What You'll Do: - You will be responsible for pre-sales support, proposing architecture to customers based on their requirements. - You will work with team to come up with architecture and micro-architecture and work with cross functional team to ensure delivery - You will manage the design / RTL team to achieve the project goals - You will work with customer, provide technical support and provide collaterals agreed upon - You will work with team to achieve flow, methodology improvements to achieve high reuse - You will work with IP vendors to generate / get right configurations of the IP - You will manage team work allocation, schedule, risk mitigation and deliverables from design team. What You'll Need: - 4+ Years of experience in understanding of ARM based architecture, CPU subsystems, interconnect, boot process, memory subsystem, knowledge of Interface IP blocks like PCIe or USB or Ethernet or DDRx controller, QSPI, DMA, or other similar blocks - Good understanding of IPs, integration/application requirement, work with RTL team/vendors to achieve architecture goals - Should have designed one or more ARM based ASIC/SoC and used one or more of PCIe, DDRx, USB, SATA, . - Should have good knowledge of multiple flavors of AMBA bus protocols & interconnect solutions available - Should have good understanding of process / flow to achieve power & performance goals - Should understand and work on all aspects of VLSI development from SoC architecture, micro architecture, RTL coding, RTL quality checks, silicon bring up. - Should have good understanding of requirements from physical design, FPGA, Software, DFT and verification team. - Should have handled a design from Spec to GDS-II - Track design progress, working with cross functional teams, delivering on agreed upon milestones. - Should provide mentoring and support to the team

Design and execute post silicon validation tests for SSD Chipsets, during R&D processes. Develop, port and execute bare metal SW to validate Storage SoCs. Job will involve Pre and Post Si testing of the bare metal functionality of the Storage SoC, including performance, and power The candidate will also review and prepare test plans and test results documentation. Develop testing and benchmarking applications. Analyze the test results and generate professional validation reports. Provide technical support to Field Application Engineers who support customers. Provide technical support to Test Engineers who design tests for mass production. What Were Looking For Bachelor s degree in Electrical , Electronics or Computer Engineering, or a related field with 12+ years of experience. Master s degree in Electrical , Electronics or Computer Engineering, or a related field with 10+ years of experience. We are looking for hardware validation/applications engineer with experience in Solid States Drive. The candidate should have prior experience interacting with customers. Proficient in C/C++ , Arm Assembly , 64 bit Arm CPU architecture. Experience in Firmware Development under Bare Metal/Linux Environment and Debugging on SoCs for embedded Applications Understanding of SSD controller is preferred Experience in interfaces like NAND/PCIe/NVMe/DDR is a plus Expertise with typical lab tools: Emulators, Oscilloscopes, Logic Analyzers Experience in analog characterization for power and high speed characterization is an added advantage. Good communication skills in English, written and spoken. Candidate should be flexible, proactive and have the ability to work across disciplines and manage time across several demands Should be able to work on a given task independently.

Firmware Dev Generic Location: Bangalore, Hyderabad, Chennai, Pune Skills/Experience: Strong C, DS, Embedded protocols (I2C, SPI, UART, USB, Ethernet, PCI/PCIe), SoC or Microcontrller Arch, ARM Arch, relevant project level experience, Python or Shell scripting and understanding of any RTOS (Eg: FreeRTOS, Vxworks, pSoS, nucleus) or LSP Domain: Driver Developer or Verification/Validation Experience (years) : 2 to 4 years Location - Bengaluru,Hyderabad,Chennai,Pune

Analog Mixed Signal Layout Location: Bangalore, Hyderabad, Noida Skills/Experience: Independent layout development of High Speed blocks like SerDes, Rx, Tx, , PLL, ADC, LDO, Bandgap etc Strong debug skills and good communication Experience (years) : 3 - 7 Years Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

Developing and executing test plans and procedures to verify the functionality and performance of a designIdentifying and documenting design defects and issues, and working with designers and other stakeholders to address themAnalyzing test results and data to identify patterns and trends, and making recommendations for design improvementsDeveloping and implementing automated test scripts and test frameworks to improve testing efficiency and accuracyCollaborating with other engineers and stakeholders to ensure that all design requirements are properly verified and validatedCreating and maintaining documentation related to the verification and validation process, including test plans, test reports, and traceability matricesParticipating in design reviews and providing feedback on design requirements and testabilityProviding technical support and expertise to other departments, to ensure that designs are implemented correctly and meet all necessary requirements. Strong analytical and problem-solving skills, with the ability to identify areas for improvement and develop effective solutions.

Job Description: As a DE/DV Lead or Senior DE/DV, you will be responsible for driving the development, verification, and validation of complex semiconductor designs focused on multi-core processors, GPUs/AI Tensors, IoT, and cutting-edge protocols. You will collaborate closely with cross-functional teams, including architecture, design, and system engineering, to ensure the successful execution of projects. Your expertise in design verification (DE) and validation (DV) will be instrumental in ensuring the functionality, performance, and quality of our semiconductor products. The key responsibilities for these roles include, but are not limited to: Key Responsibilities: Lead the design verification and validation efforts for multi-core processors, GPUs/AI Tensors, IoT, and related protocols. Define verification/validation strategies, methodologies, and test plans to ensure comprehensive coverage. Develop and execute advanced verification/validation environments and testbenches. Perform functional and performance verification/validation tests, analyze results, and drive issue resolution. Collaborate with design and architecture teams to address design issues and refine specifications. Drive the development of advanced verification/validation techniques and methodologies. Mentor and provide technical guidance to junior team members. Stay updated with the latest industry trends, emerging technologies, and protocols related to the target domains. Collaborate with cross-functional teams to ensure successful project execution and timely delivery. Qualifications: Bachelor s, Master s, or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. Proven experience in design verification and validation of complex semiconductor designs. Strong expertise in multi-core processors, GPUs/AI Tensors, IoT, and related protocols. In-depth knowledge of verification/validation methodologies, testbench development, and coverage-driven verification. Proficiency in using industry-standard verification/validation tools and languages (e.g., SystemVerilog, UVM). Experience with protocols such as PCIe Gen 6, Cache coherence/CXL 3.0, DDR5/GDDR5/LPDDR/HBM. Strong analytical and problem-solving skills. Excellent communication and collaboration abilities. Leadership skills for DE/DV Lead positions. Company Overview: Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. If you are a talented and experienced DE/DV Lead or Senior DE/DV with a passion for multi-core processors, GPUs/AI Tensors, IoT, and cutting-edge protocols, we invite you to apply for this role at AISemiCon. To apply, please submit your resume and a cover letter highlighting your relevant experience and achievements to hiring@aisemicon.in We look forward to reviewing your application and discussing how you can contribute to our mission of advancing high-performance computing. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs.

Job Description: As a Platform IOMMU Architect, you will play a critical role in driving acceleration from the Linux perspective. Your primary focus will be on designing and implementing IOMMU solutions that optimize data transfer and memory access in the PCIe context. Understanding different modes, such as DMA translation and Passthrough, will be crucial to your success in this role. You will work closely with cross-functional teams to drive architecture design, considering practical challenges, microarchitecture, and RTL implementation. We are looking for individuals who can bring a practical perspective to architectural decisions and possess strong knowledge of Linux environments. The key responsibilities for this role include, but are not limited to: Key Responsibilities: Drive the architecture and design of Platform IOMMU solutions for Linux-based systems. Understand and leverage different modes (DMA translation and Passthrough) in the PCIe context. Collaborate with cross-functional teams to ensure efficient and reliable data transfer and memory access. Consider practical difficulties and challenges when arriving at microarchitecture and RTL implementation. Analyze and optimize performance, latency, and throughput in IOMMU designs. Work closely with hardware and software teams to ensure seamless integration and compatibility. Stay updated with the latest advancements in IOMMU technology, PCIe specifications, and Linux developments. Provide technical guidance and support to the development team. Drive innovation by exploring new techniques and emerging technologies in IOMMU acceleration. Qualifications: Bachelor s, Master s, or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. Proven experience as an architect or engineer in designing Platform IOMMU solutions. Strong understanding of IOMMU concepts, PCIe architecture, and Linux environments. Experience with different modes, including DMA translation and Passthrough, in the context of PCIe. Proficiency in microarchitecture design and RTL implementation for IOMMU solutions. Solid knowledge of data transfer, memory access optimization, and performance analysis. Familiarity with hardware/software co-design and integration processes. Excellent problem-solving and analytical skills. Effective communication and collaboration skills. Company Overview: Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. If you have the expertise in driving acceleration in Linux environments and possess a deep understanding of Platform IOMMU, we encourage you to apply for the position of Platform IOMMU Architect at AISemiCon. To apply, please submit your resume and a cover letter highlighting your relevant experience and achievements to hiring@aisemicon.in We look forward to reviewing your application and discussing how you can contribute to our mission of advancing high-performance computing. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs.

Who You ll Work With Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscale datacenters and bleeding edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments. What You ll Do: As a Hardware Board Design Engineer at Arista, you ll be responsible for the complete hardware design process, including authoring functional specifications, schematic capture, and collaborating with eCAD teams on PCB layout. You ll select and qualify components, specify PCB stackup and fabrication details, and work closely with contract manufacturers through the prototype and production phases. Additionally, you will lead lab bring-up, debug complex systems, and work cross-functionally with software and test teams. Mentoring junior engineers and ensuring high yield in manufacturing will also be key aspects of your role. Job Responsibilities Candidates for this position would be responsible for the entire hardware design process: Authoring Functional Specifications for high density Ethernet switches Selecting and Qualifying Components Schematic Capture (both flat and hierarchical) Working closely with eCAD teams on PCB layout and component footprints Specifying PCB stackup and fabrication details with various PCB vendors Working closely with local and overseas Contract Manufacturers (CM), from proto through production Lab bring up and debug of prototypes Driving complex system debug between software, hardware, and test teams Training CM for high yield test and manufacturing Guiding groups of engineers and mentoring younger engineers BSEE or MSEE 5+ years of relevant experience in hardware engineering Embedded x86/ARM system design is highly desirable Experience working with multi-phase DC/DC s for high current, high transient loads Experie

Who You ll Work With Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscale datacenters and bleeding edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments. What You ll Do: You ll lead the hardware design process for high-performance networking products, from creating functional specifications and schematic design to collaborating with eCAD teams on PCB layout. You ll work with PCB vendors, oversee prototypes through to production, and ensure high yield in manufacturing. Additionally, you ll troubleshoot system issues with software and test teams, while mentoring junior engineers to drive innovation in high-speed networking solutions. Job Responsibilities Candidates for this position would be responsible for the entire hardware design process: Authoring Functional Specifications for high density Ethernet switches Selecting and Qualifying Components Schematic Capture (both flat and hierarchical) Working closely with eCAD teams on PCB layout and component footprints Specifying PCB stackup and fabrication details with various PCB vendors Working closely with local and overseas Contract Manufacturers (CM), from proto through production Lab bring up and debug of prototypes Driving complex system debug between software, hardware, and test teams Training CM for high yield test and manufacturing Guiding groups of engineers and mentoring younger engineers BSEE or MSEE 5+ years of relevant experience in hardware engineering Embedded x86/ARM system design is highly desirable Experience working with multi-phase DC/DC s for high current, high transient loads Experie

As a Systems Architecture Lead you will be responsible for systems and product architecture development for advanced Application Processors. You will work across hardware engineering, software engineering, application/solutions engineering teams to design and develop best in class, scalable, robust solutions that meet the demanding requirements of our advanced microprocessor products for Industrial, IOT, and Automotive Edge markets. This role requires a deep technical understanding of MPU HW & SW architecture, Solutions Engineering, Use Case Analysis, Validation, Optimization, and system integration. Key Responsibilities: Drive the definition and development of MPU architecture, ensuring alignment with market trends and industry standards. Work with product marketing teams and customers to understand and translate requirements into detailed specification. Drive use case definition and documentation for the product. Define scalable and efficient computing architectures, including multi-core processing, high end CPU, DSP, Vision processing, Machine Learning, and memory hierarchy. Design and integrate security mechanisms, including secure boot, cryptographic accelerators, and trusted execution environments. Collaborate with hardware, firmware, software, solutions/application engineering teams to ensure seamless system-level integration of MPU product components. Power and performance benchmarking, analysis, and optimization. Develop strategies to optimize performance, energy efficiency, and thermal management while maintaining reliability and scalability. Own key performance indicators for programs and drive optimization. Define architectural guidelines, best practices, and documentation to guide product development teams. Required Qualifications: Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or related field with 15 years or more relevant experience. Experience with use-case analysis and decomposition. Experience in Linux, Zephyr, Free RTOS or similar operating systems. Strong understanding of microprocessor and microcontroller architectures, including CPU cores, DSP, memory management, and peripheral integration. Experience with system level performance optimization, low-power design, SW/HW co-design, and real-time processing. Familiarity with high-speed interconnects, memory architectures, DDR, PCIe, and bus protocols. Strong collaboration skills to work across multidisciplinary teams, including silicon, software, hardware, board design, and validation engineers. Experience in product development processes. Preferred Qualifications: Experience with ARM Cortex and/or RISC-V architecture. Experience with media processing, vision and imaging applications. Experience with system-level simulation tools, hardware/software co-design, and debugging techniques. Familiarity with Machine Learning Hardware IPs, tools, and architecture. Knowledge of functional safety and security standards. Familiarity with Wi-Fi integration, networking protocols, and secure wireless communication. More information about NXP in India... #LI-6825

SOC Verification engineers with 3+ years of experience Knowledge of ARM architecture, CPU fundamentals & Cache coherency Experience with C/C++, assembly, and scripting languages. Familiarity with low-power design and verification Develop CDV UVM verification environments at system level Verify CPU connectivity to IP blocks Develop SoC test plans and test cases and track metrics including code and functional covera Job Requirement: Bachelors or Masters in EE/CS or related field 3+ years of SoC in ASIC/FPGA verification experience Proficiency in SV and UVM Experience with simulation, emulation, and formal verification Strong debugging and problem-solving skills Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Analog Circuit Simulations Location: Bangalore, Hyderabad, Noida Skills/Experience: Proficient in analog circuit simulations and characterisation for blocks like SerDes Rx Tx Strong fundamentals and knowledge of high-speed custom digital Experience (years) : 2+ Year Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : BE/ME/Btech/ Mtech in computer science eng or electronics and Communications. The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/ Reset/Fabrics, DfD, Fuse, etc) with experience in CDC, linting, spyglass, micro-architecture. Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 3 to 8 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/ Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools & flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods.

Proficient in RTL design using Verilog/SystemVerilog or VHDL In-depth knowledge of FPGA architecture and development flows (synthesis, P&R, timing analysis) Familiarity with high-speed interfaces and protocols like PCIe, Ethernet, DDR, AXI, AHB, SPI Required Candidate profile Experience with debugging tools like ChipScope, SignalTap, Logic Analyzer Proficiency in scripting languages like Python, Tcl, or Perl for automation of FPGA workflows

Knowledge on verification plans based on design specifications and requirements Proficiency in UVM and SystemVerilog for developing verification environments Unterstanding of protocols like PCIe, USB, Ethernet, or AMBA (AXI, AHB, APB) Required Candidate profile Hands-on experience with debugging tools like Verdi, DVE, or SignalTap Ability to analyze and resolve complex design and verification issues Proficiency in scripting languages like Python, Perl, Shell

About The Role Role and Responsibilities You will be part of Intel Core Design Team driving Intel's latest CPUs in the World's leading process technologies. Develops pre-Silicon functional verification tests to verify system to meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify test bench and tests. We're looking for a highly motivated, Pre-Silicon Verification Engineer who is responsible to ensure: Development of Complex Pre-Silicon Verification environment Development of Verification Components and coverage plans Write and execute validation Plans to ensure Right First Time Success of our Products Work directly with hardware architects, logic designers to influence overall SoC and system design. Qualifications Qualifications Candidatemust possess a master's degree in Electronics or Computer Engineering with at least 8+ or more years of experience in related field. Preferred Qualifications: Experience in Processor verification Experience with Specman/SV Language is plus Experience in verifying Power Mgmt, Cache controllers and memory features is plus Experience with Formal verification techniques is a plus Strong background in scripting- PERL/Python System hardware and software debug skills Understanding of software and/or hardware validation techniques Solid understanding of system and processor architecture, and the interaction of computer hardware with software. Candidate should demonstrate excellent Self-motivation, communication, strong problem solving, excellent in cross-site communication and teamwork skills. Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core „¢, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

About The Role Develops pre silicon functional validation tests to verify system will meet design requirements Creates test plans for RTL validation defining and running system simulation models and finding and implementing corrective measures for failing RTL tests Analyzes and uses results to modify testingKnowledge of Verilog ,System Verilog, UVM Based Testbench developmentUnderstanding of code functional coverage system Verilog assertion codingGeneral Scripting and programming skills Python Per TCL etcFormal verification would be a plusIP Level testbench development using SV and UVMTestplan development using Verification planner, tracking and closer of code and functional coverageReq LocationSRR4 Bangalore About The Role Your responsibilities include but are not limited to: Define and develop test env to verify the IP/Sub System functionality. Define Test plans and develop Tests contents.Define Checkers/monitors strategy. Define and Develop Assertions.Define Cover points and analyze functional coverage with analysis. Define Volume regressions strategy and run simulations followed by failure debugs. Develop formal verification assertions, properties. Define and perform Performance Verification. Mentoring and coaching junior verification engineers. Leadership to manage stake holders with end to end objectives in mind. The candidate should have ability to work effectively with both internal and external teams/stakeholders. Should possess strong problem solving/communication skills. Should be a very good team player. Qualifications QualificationsYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:Candidate should possess a Bachelor's degree in Electrical, Electronics, Computer Engineering or Computer Science or any related field with 7+ years' experience -OR - a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 5+ years experience -OR- PhD degree in Electrical, Electronics, Computer Engineering or Computer Science or any related field with 3+ years experience in:VLSI design.Verification/validation tests.Expertise in System Verilog/C++/OVM or UVM methodology and/or Formal Verification techniques.Preferred qualification:System simulation models, and debugging RTL/tests.Experience with Cache Coherency protocols or PCIE/CXL would be a huge plus Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications :- are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Requirements listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or school. work/classes/research. Education Requirement:- Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 9 years of industry work experience, or- Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 7 years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 5 years of related work experience.Minimum Qualifications:- 8+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth know how. Solid work experience in designing, verifying, and validating complex hardware systems.Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, and Python.Proficient in debugging SOC, fabric, NOC, memory, various protocols like PCIE or Ethernet, or other complex ASIC designs.Knowledge of advanced computer architecture and micro-architecture concepts.Experience with writing directed and random test cases.Experience with design verification and validation methodologies and strategies.Good communication skills, and a team player.Able to work independently in a fast-paced team and environment. Desired Requirements- Deep knowledge of system architecture including CPU, Data path packet processing flows , Boot Flows, fabrics, interconnects, NOC, memory sub-systems, I/O peripherals (UART/SPI), bus protocols (AXI/APB), PCIE, Ethernet, DMA, CSRs, etc. MACsec , Time-Sensitive Networking (TSN) Experience with boot, reset, clock, and power management. Inside this Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

SmartSoC Solutions is looking for Design Verification Engineer to join our dynamic team and embark on a rewarding career journey. Developing and executing test plans and procedures to verify the functionality and performance of a designIdentifying and documenting design defects and issues, and working with designers and other stakeholders to address themAnalyzing test results and data to identify patterns and trends, and making recommendations for design improvementsDeveloping and implementing automated test scripts and test frameworks to improve testing efficiency and accuracyCollaborating with other engineers and stakeholders to ensure that all design requirements are properly verified and validatedCreating and maintaining documentation related to the verification and validation process, including test plans, test reports, and traceability matricesParticipating in design reviews and providing feedback on design requirements and testabilityProviding technical support and expertise to other departments, to ensure that designs are implemented correctly and meet all necessary requirements. Strong analytical and problem-solving skills, with the ability to identify areas for improvement and develop effective solutions.

Embedded Developer Job ID: # 202503 C/C++ coding skills with Embedded SW/FW in microcontrollers, microprocessors in BareMetal, RTOS, Linux, etc. Strong understanding of Embedded CPU Architecture, peripherals, protocols, memory devices. Proven experience in developing bootloaders, drivers for peripherals, protocols. Experienced in debugging at device drivers, data transfers across peripherals, state machines, etc. Good knowledge of high-speed (PCIe/Ethernet/USB, etc.) and low-speed I/O buses (SPI/I2C/I3C/UART/SMBus). Familiarity with hardware debugging tools and techniques. Working experience with SDLC process (version control, code review, bug tracking mechanisms). We are also interested in the BOT model if you are into that apart from staffing mode. We can have further discussions if required. Company: Location: Bangalore Company Size: 1-20 Job Type: Contract Date: 5 to 7 Years Requirements

Who You ll Work With Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscale datacenters and bleeding edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments. What You ll Do: You ll lead the hardware design process for high-performance networking products, from creating functional specifications and schematic design to collaborating with eCAD teams on PCB layout. You ll work with PCB vendors, oversee prototypes through to production, and ensure high yield in manufacturing. Additionally, you ll troubleshoot system issues with software and test teams, while mentoring junior engineers to drive innovation in high-speed networking solutions. Job Responsibilities Candidates for this position would be responsible for the entire hardware design process: Authoring Functional Specifications for high density Ethernet switches Selecting and Qualifying Components Schematic Capture (both flat and hierarchical) Working closely with eCAD teams on PCB layout and component footprints Specifying PCB stackup and fabrication details with various PCB vendors Working closely with local and overseas Contract Manufacturers (CM), from proto through production Lab bring up and debug of prototypes Driving complex system debug between software, hardware, and test teams Training CM for high yield test and manufacturing Guiding groups of engineers and mentoring younger engineers BSEE or MSEE 5+ years of relevant experience in hardware engineering Embedded x86/ARM system design is highly desirable Experience working with multi-phase DC/DC s for high current, high transient loads Experience working with high speed interfaces, such as DDR, PCIe Writing specifications and drawing schematics for high complexity boards Working closely with CAD designers on complicated layout and routing Working closely with Software and test engineers to bring-up and debug systems Experience with mass production Design for Manufacturability (DFM) Working with Contract Manufacturers Successfully taking products from concept to production

Who You ll Work With Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscale datacenters and bleeding edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments. What You ll Do: As a Hardware Board Design Engineer at Arista, you ll be responsible for the complete hardware design process, including authoring functional specifications, schematic capture, and collaborating with eCAD teams on PCB layout. You ll select and qualify components, specify PCB stackup and fabrication details, and work closely with contract manufacturers through the prototype and production phases. Additionally, you will lead lab bring-up, debug complex systems, and work cross-functionally with software and test teams. Mentoring junior engineers and ensuring high yield in manufacturing will also be key aspects of your role. Job Responsibilities Candidates for this position would be responsible for the entire hardware design process: Authoring Functional Specifications for high density Ethernet switches Selecting and Qualifying Components Schematic Capture (both flat and hierarchical) Working closely with eCAD teams on PCB layout and component footprints Specifying PCB stackup and fabrication details with various PCB vendors Working closely with local and overseas Contract Manufacturers (CM), from proto through production Lab bring up and debug of prototypes Driving complex system debug between software, hardware, and test teams Training CM for high yield test and manufacturing Guiding groups of engineers and mentoring younger engineers BSEE or MSEE 5+ years of relevant experience in hardware engineering Embedded x86/ARM system design is highly desirable Experience working with multi-phase DC/DC s for high current, high transient loads Experience working with high speed interfaces, such as DDR, PCIe Writing specifications and drawing schematics for high complexity boards Working closely with CAD designers on complicated layout and routing Working closely with Software and test engineers to bring-up and debug systems Experience with mass production Design for Manufacturability (DFM) Working with Contract Manufacturers Successfully taking products from concept to production

Experience: 2+ years. Requirements: Bachelor s/Master s degree in Electronics, Electrical, or a related field. 2+ years of experience in PCB design using Altium Designer . Strong understanding of high-speed design principles and multi-layer PCB routing. Experience with CAN, LIN, USB, Ethernet, PCIe, LVDS, and RGB interfaces . Knowledge of power routing techniques for stable and efficient designs. Familiarity with IPC standards for footprint creation and PCB layout. Hands-on experience with signal integrity analysis and EMC/EMI considerations . Strong problem-solving skills and attention to detail. Shift details: Normal shift