665 Pcie Jobs - Page 9

Job Summary We are looking for highly skilled and efficient engineer to join our System Power, Thermal and Performance team. The candidate will have hands-on experience in executing CPU, GPU, and AI/ML workloads on Android and Windows platforms, o with a strong understanding of SoC subsystems and performance/power KPIs. This role involves system validation, power and performance measurements and optimization, automation, data analysis and handling lab equipment Key Responsibilities Execute and analyze CPU/GPU/AI-ML workloads and benchmarks on Android and Windows platforms Run and interpret power, thermal and performance KPIs from CPU/GPU synthetic workloads and system benchmarks. Execute and collect power and performance KPIs from MLPerf, GenAI models, Vision workloads Collect logs and profiling data from different SoC subsystems (CPU, NPU, DDR, etc.). Monitor and evaluate power and performance KPIs for dashboard generation and reporting. Develop and maintain automation scripts using Python, Shell, or Batch for data collection, parsing, and report generation. Operate lab equipment such as oscilloscopes, power analyzers, and other tools.

Key Responsibilities: Develop AMS verification environments from the ground up using SystemVerilog/UVM Own and execute test planning, AMS setup, and mixed-signal simulation Work on SerDes verification involving high-speed protocols (PCIe, USB 3.0, MIPI, etc.) Model and verify analog/mixed-signal blocks using wreal , RNM , and Verilog-A Perform simulations using VCS Primesim AMS and Primesim XA tools Collaborate closely with analog, digital, and system teams for integrated AMS verification

Required Skills : Strong Embedded C Programming abilities Hands-on experience in developing device drivers, applications using 16/32 Bit Microcontroller based platforms. Knowledge and experience in bare metal coding and RTOS. Experience with various IDEs (Ex MPLAB X IDE, STM32CubeIDE, Code Composer Studio, nRF MDK) and scripting languages (Python, Shell scripts) Experience in Embedded, Automotive Software and driver development with ARM/RISC based MCUs on BareMetal/RTOS etc., Strong Debug Skills and experience with JTAG, GDB debuggers & Lauterbach etc., Familiarity with parallel-processing concepts such as threads, signals, priorities, semaphores, mutexes, race-conditions, deadlocks, etc. Prior development experience with peripherals like USB/Ethernet/PCIe/I2C/SPI/MQTT/HTTPs etc on BareMetal/RTOS Good analytical and problem-solving skills Experience with version control tools like git, and code review tools like Collaborator, gerrit etc., Good communication, interpersonal, and teamwork skills

Project description This is a great opportunity to work as a part of a highly regarded team to deliver leading-edge solutions. We are looking for an experienced engineer for an exciting role to augment our Client's core Linux-embedded team to work on the latest platforms and software. The person will interact closely with key technical experts to ensure the best possible performance and results on the SoC platforms. Responsibilities Design, develop, and maintain x86 BIOS/UEFI firmware, ensuring robust and efficient solutions aligned with project specifications. Collaborate with hardware and software teams to support x86 CPU/APU architectures, optimizing performance through expert-level C programming. Work on UEFI bootloaders and applications, focusing on UEFI-based storage protocols such as AHCI, SATA, and NVMe. Perform platform hardware analysis and interpret processor specifications to support coreboot mainboard porting and integration. Integrate and customize BIOS code bases (AMI, Insyde, or Phoenix BIOS) to meet customer and platform requirements. Debug and resolve firmware-related issues, leveraging deep knowledge of UEFI framework concepts and storage protocols. Contribute to the development of Android UEFI-based bootloaders for x86 platforms, if applicable. Maintain code quality through rigorous testing, documentation, and adherence to best coding practices. Provide technical guidance and mentorship to junior developers, supporting knowledge sharing and team growth. Collaborate with cross-functional teams to ensure smooth firmware delivery, addressing technical challenges proactively. Skills Must have 5-15 years of experience in the x86 BIOS/UEFI development Experience with x86 CPU/APU architectures and associated compilation tools Expert in C language Familiar with at least one BIOS code base (AMI, Insyde, or Phoenix BIOS) Experience working on UEFI bootloader or UEFI applications mainly involved in UEFI-based storage protocols AHCI, SATA, and NVMe. Will be good if have any experience in Android UEFI-based Bootloader for x86. Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required. Good understanding of UEFI framework concepts and Storage protocols. Nice to have Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. Good understanding of industry-standard protocols like SATA, NVMe, AHCI, PCIe, SPI, eSPI etc. Good understanding of specifications like ACPI, SMM. Good understanding of x86-64 architecture from BIOS developer's perspective. Good understanding of UEFI BIOS Boot flow. Bachelor's degree in computer science engineering from a reputed college Master's degree from a reputed university is a big plus

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, particularly using industry-standard protocols and methodologies, this role offers a challenging opportunity for individuals well-versed in System Verilog, Verilog, and Object-Oriented Programming. As a successful candidate, you will have demonstrated your ability to lead the development of reusable Verification environments on at least 2 projects using VMM, OVM, or UVM methodologies. Your expertise should extend to protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development and updates, and collaborating with Architects and methodology experts to address issues and drive architectural and methodological perspectives. If you are a proactive and reliable professional with a passion for Verification, we invite you to share your updated CV with us at taufiq@synopsys.com. Feel free to refer anyone who may be interested in this exciting opportunity as well. At Synopsys, we value Inclusion and Diversity, considering all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Join us in shaping the future of technology.,

The position of Technical Lead ASIC Design Verification requires the candidate to have direct experience in managing a 4-10 member engineering team and servicing clients in Project (ODC) based execution model as well as Staffing (Hyderabad Onsite requirements). The role involves Architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to various customer products. The incumbent will lead an IP Verification team and provide technical leadership to the Design Verification team. Effective team management, coaching, mentoring, and career planning are essential responsibilities. The incumbent must lead management and customer reviews for multiple projects and develop/modify scripts to automate the verification process. The candidate should have a minimum of 6 years of experience in System Verilog HVL and OVM/UVM/VMM/Test Harness. Hands-on experience in developing assertion, checkers, coverage, and scenario creation is required. Experience in executing at least 2 to 3 SoC Verification projects, developing test and coverage plans, verification environments, and validation plans is necessary. Knowledge of industry-standard protocols like Ethernet, PCIe, MIPI, USB, or similar is expected. The candidate should have at least 1 year of experience in handling a team of 5 to 10 engineers. Defining/deriving scope, estimation, schedule, and deliverables of proposed work, ensuring resource compatibility, and working with customers through acceptance of deliverables are also key responsibilities. This is a Work from Office job, and the incumbent should have the willingness and experience to lead and mentor junior engineers. The educational background required for this position is B.E./B.S./B.Tech/M.S./M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering. eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services with a proven track record of over 25 years. With a team of over 2500+ engineers, the company has been instrumental in developing over 500+ products and 40M deployments in 140 countries. eInfochips offers Silicon Engineering, Embedded Engineering, Hardware Engineering & Digital Engineering services and is recognized as a leading Semiconductor service provider by NASSCOM, Zinnov, and Gartner.,

As a Systems Architecture Lead, you will be responsible for the development of systems and product architecture for advanced Application Processors. Your role will involve collaborating with hardware engineering, software engineering, application/solutions engineering teams to design and create scalable, robust solutions for our advanced microprocessor products targeting Industrial, IOT, and Automotive Edge markets. A deep technical understanding of MPU HW & SW architecture, Solutions Engineering, Use Case Analysis, Validation, Optimization, and system integration is essential for this role. Your key responsibilities will include driving the definition and development of MPU architecture in alignment with market trends and industry standards. You will work closely with product marketing teams and customers to translate requirements into detailed specifications. Furthermore, you will be responsible for defining scalable computing architectures, integrating security mechanisms, collaborating with cross-functional teams, and optimizing power and performance benchmarks. To qualify for this role, you should hold a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field with 15 years or more of relevant experience. Additionally, experience in use-case analysis, Linux, Zephyr, Free RTOS or similar operating systems, microprocessor and microcontroller architectures, system-level performance optimization, low-power design, SW/HW co-design, and real-time processing is required. Strong collaboration skills and familiarity with high-speed interconnects, memory architectures, bus protocols, and product development processes are also necessary. Preferred qualifications include experience with ARM Cortex and/or RISC-V architecture, media processing, vision and imaging applications, system-level simulation tools, Machine Learning Hardware IPs, functional safety, and security standards. Familiarity with Wi-Fi integration, networking protocols, and secure wireless communication would be advantageous. In this role, you will play a crucial part in designing and developing cutting-edge solutions for advanced microprocessor products, contributing to the success and innovation of our products in Industrial, IOT, and Automotive Edge markets.,

As a SoC RTL Design Engineer at Lattice Semiconductor, you will join the HW design team focused on IP design and full chip integration. This exciting position offers the opportunity to be part of a dynamic team where you can contribute, learn, innovate, and grow. Located in Pune, India, this full-time role will concentrate on RTL design, full chip integration, and projects within similar time zones, providing ample opportunities to work on cutting-edge technologies. Your responsibilities will include working on RTL design with best-in-class coding styles, algorithms, and utilizing Verilog and System Verilog. You will also be involved in SoC integration and quality checks such as lint, CDC, RDC, SDC, etc. Collaborating closely with the architect and micro-architect team, you will define design specifications and work towards accelerating design time and improving quality through logic design of key blocks and full chips. To be successful in this role, you should have a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science, or equivalent, along with at least 5 years of experience in driving logic design across various silicon projects. Expertise in SoC integration, defining micro-architecture, and experience with 3rd party IP selection is required. Additionally, familiarity with FPGA designs, ARM processor, AXI, AMBA bus, ENET, PCIE, safety and security protocols, and debug architecture will be advantageous. You should be an independent worker and leader with strong problem-solving abilities, capable of working with multiple groups across different sites and time zones. Occasional travel may be required as part of the role. Lattice Semiconductor values its employees and offers a comprehensive compensation and benefits program to attract, retain, and reward top talent in the industry. Lattice Semiconductor is a service-driven developer of innovative low-cost, low-power programmable design solutions with a global workforce that is dedicated to customer success and driven to achieve excellence. If you are passionate about working in a fast-paced, results-oriented environment and believe you can thrive in a demanding yet collegial atmosphere, Lattice Semiconductor may be the perfect fit for you. Feel the energy at Lattice Semiconductor.,

As a Linux Development Engineer, you will be responsible for bringup of IBM Power Hardware. You will apply your deep expertise in Hardware bring-up process, PCIe, Root Complex during your journey at the Linux Technology Center. You will also interact with opensource communities to upstream your work as well as work in close collaboration with hardware teams. This includes Bringup of new versions of Power Hardware on Simulators/QEMU, Hardware Configurations bring-up, PCIe/PHB Bring-up, Inband communication with BMC, System dump management, JTAG debugging, XIVE interrupt controllers and OpenCAPI/CXL. Required education Bachelor's Degree Required technical and professional expertise 10 to 15 years of experience in working on projects related to Hardware Bring-up Root Complex, Protocol training, Link Equalization, PCI/PCIe driver, PCI enumeration, XIVE, QEMU, PLDM, IOMMU Strong programming skills in C. Strong Operating systems skills Deep expertise in hardware bring-up / debugging. Deep expertise in computer systems architecture.

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Required technical and professional expertise -2+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Job Description As a member of the Design Verification [Pre-Silicon DV] Team for NXP WCS/SCE BU. You will be responsible for verification of various IPs and/or SoC. Candidate must be self-motivated and capable of working independently or as part of a team. You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test-plans, debugging failures and analyzing coverage information. Must have excellent knowledge of computer architecture and design verification fundamentals Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies Must have experience in developing complex test bench in System Verilog using OVM/UVM methodology Hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol Experience in Low Power Simulation/UPF setup, debug low power simulation failures. Exposure to scripting languages like Perl, Unix shell or similar languages Good to have some experience with assembly language programming required Excellent written and oral communication skills necessary.

SoC NoC Verification Engineer - Lead Experience: 10+ Years Work location: Bangalore Job Description: SoC NoC Verification Lead with 10+ years of experience, the role typically expands to include leadership, strategic planning, and advanced debugging. This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities: Lead verification projects for complex SoC and NoC architectures. Develop advanced verification methodologies using SystemVerilog/UVM. Guide teams in debugging and resolving intricate design issues. Optimize performance, power, and coverage metrics. Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Manage testbench architecture and automation frameworks Role & responsibilities Preferred candidate profile

As an Analog Design Engineer at Sykatiya Technologies, you will be an integral part of our highly talented team that focuses on Technical Ability and a positive Attitude. Your contributions to projects will reflect our commitment to excellence for our customers. Our team consists of skilled engineers and experts in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are looking for an Analog Design Engineer with 3-12 years of experience to join our team in Bangalore. The ideal candidate will have experience in transceiver design for high-speed interfaces such as DDR, HBM, PCIe, USB3, and JESD204. Exposure to nodes below 22nm is a plus, along with experience in FINFET technology and the 32G-112G range of SERDES. In this role, you will be responsible for taking at least one block from circuit design to layout closure. You should also be able to guide the layout team in high-performance matched circuit design. Understanding reliability requirements such as ESD, EMIR, EOS, Aging, and being able to work independently while mentoring junior team members are essential qualities we are looking for. If you have exposure to post-silicon validation, it would be considered a plus. Join us at Sykatiya Technologies and be part of a dynamic team that values technical expertise, a positive attitude, and a commitment to excellence in Analog Design.,

As a Director of NVEG PE Hardware (Test Platform Enablement) at Micron Technology, you will have the opportunity to lead a team of engineers in developing and qualifying cost-effective engineering test platforms. Your strategic leadership will be crucial in enabling the PE test infrastructure to test, debug, and characterize NAND components and system products. Collaboration with cross-functional teams such as Test Engineering, System Integration, ASIC, and FW teams will be essential in qualifying and ramping up cutting-edge NAND and system Micron products. Your key responsibilities will include designing, developing, and qualifying PE test hardware, platforms, firmware, and software. Collaboration with various teams to align testing efforts with business goals, providing engineering test solutions for product development, and driving the adoption of automation tools to enhance testing efficiency will be crucial aspects of your role. Additionally, you will be responsible for supporting new protocol enablement, conducting test capability gap analysis, and providing guidance on career development within your team. To excel in this role, you should possess knowledge of storage interfaces such as High-Speed ONFI, UFS, PCIe, and have an understanding of memory and storage system behavior, architecture, and design. Strong statistical knowledge, data analysis, problem-solving, and decision-making skills are essential, along with excellent organizational, communication, presentation, and leadership skills. The ability to work independently, lead cross-functional teams, and adapt to change in a fast-paced environment will be key to your success. A minimum of a Bachelors degree in Electrical, Electronics, or Computer Engineering, along with 10+ years of experience in semiconductor testing, including hardware and software knowledge, with at least 5 years in a leadership role, is required for this position. Micron Technology is a global leader in innovative memory and storage solutions, driving advancements in artificial intelligence and 5G applications. If you are self-motivated, enthusiastic, and possess the necessary skills and experience, we invite you to explore a career with us at Micron Technology, Inc. For more information, please visit micron.com/careers. If you require assistance with the application process or need reasonable accommodations, please contact hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and complies with all applicable labor laws and standards.,

As a Verification Engineer at Google, you will play a crucial role in ensuring the functionality and performance of Google's custom silicon solutions. You will be responsible for verifying digital systems, including infrastructure IP, interconnects, caches, memory management, and system services. Your expertise will be instrumental in shaping the next generation of hardware experiences, delivering unmatched performance, efficiency, and integration. Your responsibilities will include planning and executing the verification of configurable Infrastructure IPs, interconnects, and memory subsystems. You will develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). Additionally, you will create cross-language tools and scalable verification methodologies to ensure comprehensive testing coverage. To excel in this role, you should have a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. You should possess experience in verifying digital systems using standard IP components/interconnects, such as microprocessor cores and hierarchical memory subsystems. Proficiency in Design Verification Test, SystemVerilog, Verilog, Computer Architecture, System On a Chip, C, C++, and Python is required. Experience in creating and using verification components and environments in standard verification methodology, scripting languages, and software development frameworks is essential. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering or Computer Science, along with 3 years of experience in areas such as Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, or Clock and Power Controllers. Experience with building verification methodologies spanning simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is advantageous. Knowledge of Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL), performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation is also beneficial. Join our team at Google and be part of the innovation that drives the future of direct-to-consumer products. Your contributions will have a global impact, shaping products loved by millions worldwide. Embrace the opportunity to work on the verification of Google's System on a Chip (SOC) offerings, collaborating with hardware architects and design engineers to deliver cutting-edge hardware experiences. Your role will involve developing performance Virtual IP address (VIPs) for supported protocols, deploying verification stacks across diverse IPs, and building generalized system topology abstractions. Together, we will develop methodologies and tools to tackle complex challenges and advance technology for the betterment of society.,

You will be responsible for the Embedded Firmware for Ethernovia's Networking devices. This responsibility includes developing firmware that configures, controls, and monitors the communication device and interacts with the host system via device drivers to expose hardware features of the devices. As a part of the Software team, you will be responsible for architecture, design, implementation, testing and integration of the firmware rolled into Ethernovia's SDK. This firmware is built ground-up for safety critical automotive application. Also, we build products with strict adherence to Functional Safety and hence every team member is required to fit into a culture of safety and best development practices. Technical Qualifications: - Bachelors or Master's degree in Computer Science/Software or related field. - Work Experience: 3 years for Mid-level and 7 years for Senior Level position. - Strong understanding of Software Development lifecycle including Architecture, Implementation and Testing fundamentals. - Proficient in C/C++ Programming Language. Experience in Python is a plus. - Experience with Firmware, preferably for communication devices like Ethernet. - Experience with Embedded firmware, preferably for communication devices like Ethernet. - Experience with integration and testing of firmware and low-level code. - Hands-on Experience with Hardware and embedded processors, preferably for communication devices. - Expertise in efficient code practices for code footprint and performance. Nice to Have Experience with: - Experience with simulation and emulation platforms. - GNU or similar compiler, debugging suite. - Embedded programming, preferably with communication devices and hardware buses like I2C, SPI, Ethernet, USB. - Building Automotive or other safety critical systems using qualification methods/processes like MISRA, ASPICE and ISO26262. - Communication protocols like Ethernet MAC, PHY, Switching, TCP/IP, Security, Serdes, PCIe, NTB, and SR-IOV. - Code Version Control and Review tools/processes like Perforce/Git, Swarm. - Automation and DevOps tools like Jenkins. - Mixed Signal systems - Analog, Digital, Digital Signal Processing (DSP). - ARM family of processors or similar embedded processors. - Bootloaders like uboot or similar. Soft Skills: - Self-motivated and able to work effectively both independently and in a team. - Excellent communication/documentation skills. - Attention to details. What you'll get in return: - Technology depth and breadth expansion that can't be found in a large company - Opportunity to grow your career as the company grows - Pre IPO stock options - Cutting edge technology - World-class team - Competitive base salary - Flexible hours - Medical, dental and vision insurance for employees - Flexible vacation time to promote a healthy work-life balance,

We are seeking a Senior Staff Verification Engineer to lead and contribute to the functional verification of complex SoC and IP designs for next-generation AI, HPC, and data center products. The ideal candidate has extensive experience in UVM/SystemVerilog , SoC and IP-level verification, and is passionate about ensuring first-pass silicon success . This role involves defining verification strategies, developing scalable environments, and collaborating cross-functionally with architecture, design, and software teams. Experience with Virtual Modeling, SystemC, and TLM is a plus , enabling advanced verification and early system-level validation. Qualifications Required Qualifications Education & Experience B. S. /M. S. in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in IP/SoC verification with a proven track record of successful silicon delivery. Technical Expertise Deep knowledge of UVM/SystemVerilog for testbench development and verification IP integration. Strong understanding of SoC architecture and protocols such as DDR5, HBM3, PCIe Gen6, CXL 3. 0 , and other high-speed interfaces. Expertise in coverage-driven verification , constrained-random testing, and assertion-based verification. Proficient in debugging RTL, testbenches, and simulation failures using industry-standard tools. Tools & Languages Hands-on experience with simulation tools (VCS, Xcelium, Questa, etc. ), waveform viewers, coverage tools, and automation scripting (Python, Perl, TCL). Preferred/Additional Skills Virtual Modeling and System-Level Verification Familiarity with SystemC and Transaction-Level Modeling (TLM) for virtual prototyping and early system validation. Experience developing or using virtual platforms for hardware/software co-verification is a strong plus. Emulation & Prototyping Exposure to emulation platforms (Palladium, ZeBu) and FPGA-based prototyping for system-level validation and performance analysis. Software Co-verification Experience working alongside firmware/software teams for pre-silicon software validation and early driver/OS bring-up. Low-Power and DFT Verification Knowledge of power-aware verification (UPF/CPF) and DFT validation methodologies is desirable.

Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Lead Software QA Engineer for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning. For more information about Astera Labs, see www.AsteraLabs.com . Key Responsibilities Lead and scale high-performing Firmware QA teams in India. Own the full software development lifecycle, from architecture and design to testing and deployment. Develop and implement software development and QA best practices, including test automation, process monitoring, and quality metrics. Collaborate cross-functionally with hardware, product, and customer-facing teams to define and deliver robust software solutions. Communicate regularly with global customers including Hyperscalers and Tier 1 OEMs to provide updates, support audits, and resolve escalations. Help build large-scale test farms and automation frameworks. Mentor, coach, and grow engineering talent through effective performance management and career development. Drive continuous improvement in team efficiency, quality, and delivery. Basic Qualifications : Bachelor s degree in Electrical Engineering or Computer Science (Master s or PhD preferred). 10+ years of experience in firmware software QA. Proven ability to build and manage complete software development teams in India. Expertise in Agile software development methodologies. Deep understanding of software test methodologies, automation, and management tools. Excellent communication and interpersonal skills, especially in customer-facing roles. Strong planning, prioritization, and project management skills in fast-paced environments. Entrepreneurial, proactive mindset with a passion for innovation and customer success. Required Experience : Proficiency and demonstrated experience with ASIC based hardware systems and SQA mechanisms. Knowledge of PCIE is required. Building and scaling technical teams with a focus on collaboration and innovation. Proficient in C and Python programming. Expert-level user of Git, Jira, and Confluence. Experience defining and tracking software KPIs and quality metrics. Development and implementation of firmware design and test plans. Knowledge of hardware/software architecture and its impact on system performance. Preferred Experience : Experience with Security Development Lifecycle and FIPS certification. Familiarity with cryptographic protocols and implementation. Knowledge of memory (DDR4/DDR5/HB) technologies. Deployment of AI based SQA and FW development

We are looking for a System Software Engineer - OpenBMC Platform. The candidate will be responsible for supporting in design and development of software solutions in the areas of OpenBMC, System Management, Platform Drivers for various NVIDIA platforms HGX, MGX, DGX platforms etc. We are looking for engineers who are passionate about working on system software and firmware components, platform drivers and system manageability standards. What youll be doing: Design and implement OpenBMC Core Infrastructure and Features for GPU Server platforms. Hands-on work with bringing up BMC firmware, performance analysis, and coding various manageability features for NVIDIA s Server platforms. Design, Develop and contribute to reviews closely working with Opensource community. Influence community to enable NVIDIA features and platform requirements. Crafting solutions for errors, stats & configuration appropriate to CPU, GPU, DIMM, SSDs, NICs, IB, PSU, BMC, FPGA, CPLD, etc. for enterprise readiness of NVIDIA Server platforms. Designing and developing performance-optimized active monitoring BMC solutions using DMTF Standards including MCTP, Redfish, SPDM, and PLDM specifications. Instrumenting code to ensure maximum code coverage, writing and automating unit tests for each implemented module, and maintaining detailed unit test case reports. Providing software quality reports based on static analysis, code coverage, CPU load. Working with security team to ensure developed code is in line with product security goals, and with hardware, teams to influence hardware design and review HW architecture & schematics. What we need to see: Bachelor of Science Degree (or higher) or equivalent experience in Computer Science, E&C and Electrical Engineering. 3+ years of relevant experience. Domain expertise in BMC Firmware development on X86 or ARM Platforms including BMC-BIOS communication, thermal management, power management, firmware update, device monitoring, firmware security, etc. Board Bring-up expertise with hands-on experience in Device drivers like I2C/I3C, SPI, PCIe, SMBus, Mail-box, etc. as well as the device trees for U-Boot and Linux kernel. OOB or In-band System Management experience with exposure to standards IPMI, KCS, DMTF Standards (PLDM, MCTP, Redfish, PMBus, NVMe, etc. ) Understanding of REST architecture style especially JSON over HTTPS with OAuth. Strong programming and scripting skills using C/C++, Bash, Python, Go, etc. both for Linux user-space programs and system programs with thorough code reviewing skills. Strong in Linux fundamentals, various Linux distributions and packages, Linux upgrade mechanisms, building and deploying Linux images. You should possess excellent written and oral communication skills, good work ethics, a high sense of collaboration, a love to produce quality work, and a commitment to finish your tasks every single day. You are a self-starter who loves to find creative solutions to complicated problems. Ways to stand out from the crowd: Contributor to industry standards like Open Compute, OpenBMC, IPMI, DMTF Standards, and open source. Expertise in system software and platform security for x86/ARM-based Rack/Blade server systems.

Drive Architecture that will define the SOC/MCU architecture and detailed technical specifications from product requirements provided by business and product marketing organizations. Collaborate closely with product and software architects to define and refine SoC-level architecture Play a key role in shaping the microarchitecture of complex IP blocks and SoC subsystems Work closely with functional verification teams on test-plan development and reviews Collaborate with other functional teams including Design, Validation, DFT, physical design and emulation teams to achieve architectural goals and performance targets Provide support to functional validation teams in post silicon debug IP selection and make/buy decisions are a key factor for this role Qualifications Strong communication skills (written and verbal), problem solving, teamwork, attention to detail, commitment to task, and quality focus BTech/MTech in Electrical / Electronic / Computer / Hardware Engineering with experience of 12+ years Can do attitude, openness to new environment, people and culture Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency Experience with benchmarking IP/SoC performance and tuning IP/SoC architecture Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Experience in using Virtual Prototype tools (ARM Fast Models, Synopsys Virtualizer, Windriver SIMICS etc. . ) is a plus

Job Summary We are seeking a Principal Post-Silicon Validation Engineer to lead the system-level validation, debug, and bring-up of complex SoCs for cutting-edge AI, HPC, automotive, MCU and data center products. In this senior role, you will drive post-silicon validation strategy , coordinate across hardware and software teams, and ensure the delivery of high-quality, production-ready silicon . Experience with Virtual Modeling, SystemC, and TLM is a plus , supporting pre-silicon co-validation and accelerating silicon bring-up. Key Responsibilities Post-Silicon Validation Planning & Execution Define and lead comprehensive post-silicon validation plans , including functional validation, performance tuning, stress testing, and interoperability . Develop and execute system-level test content , leveraging real-world workloads, benchmarks, and custom test suites. Drive silicon bring-up , working closely with cross-functional teams to ensure first-pass success. Silicon Debug & Issue Resolution Lead complex issue triage, debug, and root cause analysis using hardware debug tools (logic analyzers, protocol analyzers, JTAG, trace). Interface with design, verification, and firmware teams to resolve issues found in silicon and drive corrective actions. Collaboration & Cross-Functional Coordination Work closely with design, verification, firmware, software, and system teams to align validation goals and schedules. Provide critical feedback to architecture and design teams on silicon behavior and feature readiness. Validation Infrastructure Development Develop and enhance validation frameworks, automation scripts, and post-silicon diagnostics to accelerate validation cycles. Contribute to lab infrastructure setup , including platform bring-up, test environments, and debug tool integration. Leadership & Mentorship Lead technical reviews, debug task forces, and post-silicon readiness assessments . Mentor junior engineers and drive a culture of technical rigor and innovation . Qualifications Required Qualifications Education & Experience B.S./M.S. in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in post-silicon validation, hardware bring-up, or related SoC/system validation roles. Technical Expertise Proven track record of silicon bring-up and validation for complex SoCs or silicon systems. Strong understanding of SoC architecture, high-speed interfaces (PCIe Gen5/6, CXL, DDR5, HBM3) , and embedded system design. Hands-on expertise in system-level validation , performance tuning, and debug of complex SoC designs. Debug & Validation Tools Proficient in hardware debug tools (JTAG, logic analyzers, protocol analyzers), as well as embedded software and firmware-level debugging. Experience with diagnostic software and post-silicon validation frameworks . Soft Skills Excellent problem-solving and analytical skills , with a methodical approach to debug and issue resolution. Strong communication and collaboration skills to work across multi-disciplinary teams.

We are seeking a Principal Verification Engineer to lead the functional verification of complex SoCs and IP blocks for next-generation high-performance computing (HPC), AI acceleration, and data center products. The ideal candidate will have deep experience in SoC/IP functional verification , UVM/SystemVerilog , and coverage-driven methodologies , with a strong focus on ensuring first-pass silicon success. In this leadership role, you will drive end-to-end verification strategy , collaborate cross-functionally with architecture and design teams, and influence product definition through early design engagement. Experience in Virtual Modeling, SystemC, and TLM is a strong plus , enabling advanced verification flows and early software co-development. Key Responsibilities Verification Planning & Execution Own the definition and implementation of IP and SoC-level verification plans , including test strategy, coverage goals, and schedule. Develop UVM/SystemVerilog-based testbenches for complex IP and SoC subsystems, focusing on scalability, reuse, and maintainability. Lead coverage closure activities, including functional, code, and formal coverage, to ensure comprehensive verification. Cross-Functional Collaboration Work closely with RTL designers, architects, firmware/software teams , and post-silicon validation to align on requirements and drive co-verification strategies. Participate in architecture and microarchitecture reviews , providing verification insights and influencing design for testability and verification efficiency. Debug & Root Cause Analysis Perform advanced debug and root cause analysis of complex functional issues, collaborating with cross-disciplinary teams to drive resolutions. Utilize industry-standard tools for waveform analysis, simulation debug, and emulation/prototyping platforms . Methodology & Process Improvement Define and drive best practices in verification methodology , including constrained-random testing, assertion-based verification, and coverage-driven approaches. Contribute to automation and regression flows , optimizing for quality and turnaround time. Technical Leadership & Mentorship Mentor junior verification engineers, guide technical reviews, and contribute to team development and growth. Champion a culture of technical excellence, innovation, and continuous improvement . Qualifications Required Qualifications Education & Experience B.S./M.S. in Electrical Engineering, Computer Engineering, or related discipline. 10+ years of hands-on experience in IP and/or SoC verification with a track record of successful silicon products. Technical Expertise Proven expertise in UVM/SystemVerilog for developing scalable, reusable verification environments. Strong understanding of complex SoC designs , including memory controllers (DDR5, HBM3), PCIe, CXL , and high-speed interfaces. Experience with coverage-driven verification and closure techniques (functional, code, assertion coverage). Solid background in debugging RTL issues , simulation-based testing, and interaction with emulation/FPGA prototyping teams. Verification Tools & Languages Proficient in simulation tools (VCS, Questa, Xcelium), waveform viewers , and scripting languages ( Python, Perl, TCL ) for automation. Familiarity with formal verification tools and techniques is a plus.

As a Silicon Design Validation Engineer at Lattice, you will have the opportunity to be part of a dynamic team working on cutting-edge FPGA projects. This role involves validating building blocks in FPGA on the board level to ensure functionality and performance according to design intent. The FPGA includes various IPs such as SERDES (PMA/PCS), Memory DDR (DDR4, LPDDR4, DDR5, etc.), DPHY, PLL, DSP, Fabric, I/O, among others. In this position, you will learn how to validate one or many building blocks within the FPGA and gain knowledge of the process and methodology required for validating IPs from planning to completion. You will work with advanced equipment, boards, and software/tools while developing validation and characterization plans for specific IPs, bench hardware, and software. You will also create test logic RTL to conduct validation and characterization tests, drive new silicon product bring-up, validation, and debug processes, and analyze data sheet parameters. The ideal candidate for this role is highly motivated to develop a career in Silicon Design Validation Engineering. You will have exposure to various areas including FPGA and its building blocks, IP validation, bench hardware and software development, and more. You will lead and manage teams, possess an electrical engineering degree, have expertise in high-speed Serdes interface characterization, high-speed board design, Verilog/VHDL, FPGA development tools, test automation development, statistical analysis concepts, and bench equipment for device characterization. To excel in this role, you should have strong written and verbal communication skills, be self-motivated, proactive, possess critical thinking skills, and demonstrate good problem-solving and debugging abilities. If you thrive in a fast-paced, results-oriented environment and are looking to contribute to a team-first organization, Lattice may be the perfect fit for you.,

As a Technical Lead or Senior Developer, you will be responsible for developing embedded software for various processors. Your expertise in developing drivers for different hardware blocks such as SSD (NVMe/SATA/SCSI), NVMeOF (NVMe over RDMA or TCP/IP), RDMA-NIC, iSCSI, NVMeOF, PCIe, RAID, and Ethernet will be crucial. Additionally, you should have a deep understanding of Linux kernel internals and experience in development based on open-source software. Exposure to different hardware/software development and debugging tools like Trace 32, JTAG, and Lacroy-PCIe Analyzer is expected. Your responsibilities will include developing high and low-level designs, drivers, and firmware for different hardware blocks. You will need to adopt operating systems and embedded software for various processor architectures, develop software based on pre-silicon development vehicles, and perform software bring-up using pre-silicon vehicles and silicon-based platforms. Upstreaming of open-source code and developing software component-level tests for integration into CI/CD systems are also part of your role. Additionally, you will be expected to debug issues using standard hardware/software-based debuggers and diagnosing equipment like Trace 32, JTAG, and Lacroy-PCIe Analyzer. To excel in this role, you should possess excellent knowledge of Linux internals and various drivers. Strong familiarity with different standards protocols such as NVMe, NVMeOF, iSCSI, RAID, PCIe, RDMA-NIC, Ethernet, and CXL is essential. A good understanding of hardware architectures in relation to the aforementioned standards is also required. Expertise in the Software Development Life Cycle (SDLC) and advanced development & debug capabilities in Firmware BSP and device drivers are crucial. You should be adept at solving complex technical problems related to system boot, UEFI, and OS functionality and be able to code to standards while integrating with existing solutions using languages like C, C++, and Python. Strong low-level debugging skills enabling root cause analysis of firmware, hardware, and OS internals are expected. Additionally, a good understanding of various CPU architectures, preferably IA, ARM, and RISC V, and the Pre-Silicon Development environment will be beneficial. Qualifications for this role include a BTech/MTech in Computers, Electronics, or Electrical Engineering and around 5 to 8 years of experience in embedded software development across different architectures.,

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. Perform design optimizations for area, power, and performance. Conduct design reviews and ensure compliance with coding standards and best practices. Work closely with verification teams to develop test plans and ensure 100% functional coverage. Debug and resolve design and integration issues during simulation and post-silicon validation. Participate in timing analysis and closure in collaboration with the physical design team. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2-10 years of experience in RTL design and implementation for VLSI systems. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. Experience in static timing analysis (STA) and timing closure workflows. Strong problem-solving skills and the ability to debug complex design issues. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: Experience with low-power design and multi-clock domain systems. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. Familiarity with machine learning or AI-based RTL optimizations. Why Join Us Work on groundbreaking projects in VLSI design and technology. Collaborate with a team of industry experts in a supportive and innovative environment. Opportunities for career growth and continuous learning. Competitive salary and benefits. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!,