458 Pcie Jobs - Page 7

The role will be a key player in organization responsible for Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence. Candidate should possess strong leadership skills with ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills, are must have attributes in this role. Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical. Minimum Qualifications & Professional Experience: 10-15 years (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing. 2-3 years of management experience leading/mentoring a small team of engineers Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/ Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers. Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience to interpret the standard s specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon. Ability to isolate the PHY and controller (MAC/PCS) features to test, develop calibration / compliance lab suites and characterize. Architect and design Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes needed to meet the performance requirements. Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus. Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures. Expertise in developing ESD/Latchup/ HTOL tests to meet industry standards reliability qualification & specification Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++

We are seeking a Senior Manager to lead our Bengaluru IC Verification team. This role offers a unique opportunity to shape the future of AI Networking. If youre a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI networking. Responsibilities Manage and lead Bengaluru team of ASIC verification engineers, fostering an inclusive and collaborative work environment. Ensure effective communication and coordination across different geographical locations. Technical Leadership in ASIC Verification: Provide technical expertise in the verification of complex ASIC designs, ensuring compliance with industry standards and project specifications. Gate Timing Simulations: Manage comprehensive gate-level simulations, including timing and power analysis, to validate the ASIC design before tape-out. RTL Coverage Analysis: Oversee the delivery of detailed coverage metrics to assess the thoroughness of the test suite. Offer actionable feedback to test writers and design engineers, focusing on identifying gaps and suggesting enhancements to broaden coverage scope. Firmware Collaboration: Work closely with Firmware teams to conduct co-simulations, ensuring seamless integration and functionality between hardware and firmware components. Team Development: Mentor and develop team members, identifying training needs and opportunities for growth. Manage third-party team augmentation in varied geographical locations. Qualification s ME/BE in Electrical Engineering, Computer Engineering, or a related field. A minimum of 12 years in ASIC verification, particularly in networking ASIC design. Technical Skills: Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, UVM) with a strong understanding of ASIC design and verification flow. Experience with coverage, gate/timing/power simulations, and test-plan documentation is required. Protocol Experience: Prior experience with Ethernet, UCIe, and PCIe protocols and both serial and parallel VIP verification modes, with strong expertise in high-speed SerDes. Leadership and Management Skills: Proven track record in managing and leading global teams with excellent people management skills, including experience in cross-cultural team dynamics. Communication Skills: Exceptional communication abilities, capable of effectively coordinating and leading a global team, and articulating complex technical issues clearly.

{"company":" About Eridu AI Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its R&D center in Bengaluru to join our world-class team. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI s solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World s leading micro-LED display company and developer of the first augmented reality contact lens) . Visit our website to learn more about our impressive list of investors, advisors and leadership team. ","role":" Position Overview We are seeking a RTL Data Path Engineer to help define and implement our industry-leading Networking IC. If youre a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. Responsibilities Data Path Design: Design and architect solutions for high-speed networking device, focusing on latency optimization, memory management, and quality of service (QoS) support. Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Conduct thorough testing and validation to ensure functionality and reliability. Performance Optimization: Analyze and optimize memory/buffering to improve performance metrics. Protocol Support: Provide support for various networking protocols and standards related to input and output queues, including Ethernet . Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including hardware engineers, firmware developers, and system architects. Qualifications BE/ME with a minimum of 8-15 years of experience. Working knowledge of system Verilog, and Verilog is Mandatory. Prior experience with ownership of memory subsystems. Proven expertise in designing and optimizing memory algorithms and QoS mechanisms, for high-speed networking devices. Solid understanding of ASIC design methodologies, including simulation, and verification tools (e.g. Synopsys, Cadence). Experience with Ethernet/PCIe networking protocols. Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues. Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences. Why Join Us? At Eridu AI, you ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. "},"

{"company":" About Eridu AI Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its R&D center in Bengaluru to join our world-class team. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI s solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World s leading micro-LED display company and developer of the first augmented reality contact lens) . Visit our website to learn more about our impressive list of investors, advisors and leadership team. ","role":" Position Overview We are seeking a Verification Engineer to join our Verification team. This role offers a unique opportunity to shape the future of AI Networking. If youre a highly motivated self-starter eager to solve real-world problems, we d love to hear from you. Responsibilities Specialized Verification Strategy: Develop verification infrastructure and test cases for ASICs in the area of network fabrics, leveraging your extensive experience in networking. Technical Expertise in ASIC Verification: Provide technical leadership in the verification of complex ASIC designs, ensuring compliance with industry standards and project specifications Gate & Timing simulations: collaborate with the team to execute comprehensive gate-level simulations, including timing and power analysis, to validate the ASIC design before tape-out. RTL Coverage Analysis: deliver detailed coverage metrics to assess the thoroughness of the test suite. Offer actionable feedback to design engineers, focusing on identifying gaps and suggesting enhancements to elevate test effectiveness and broaden coverage scope. Quality Assurance and Process Optimization: Uphold the highest standards of verification quality. Initiate and implement process improvements for increased efficiency and effectiveness. Qualifications ME/BE in Electrical Engineering, Computer Engineering, or related field. Experience: A MINIMUM of 8-15 years in ASIC verification in the area of data center networking. Technical Skills: Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, UVM) with a strong understanding of ASIC Design and Verification flow. Experience with coverage, gate/timing/power simulations & test-plan documentation is required. Prior experience with Ethernet and PCIe Protocols and Serial and Parallel VIP verification modes. Strong prior experience with High speed Serdes. Communication Skills: Exceptional communication abilities, capable of effectively coordinating, and articulating complex technical issues in a clear manner. Why Join Us? At Eridu AI, you ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. "},"

{"company":" About Eridu AI Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its R&D center in Bengaluru to join our world-class team. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI s solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World s leading micro-LED display company and developer of the first augmented reality contact lens) . Visit our website to learn more about our impressive list of investors, advisors and leadership team. ","role":" Position Overview We are seeking an RTL Packet Processing Engineer to help define and implement our industry-leading Networking IC. If youre a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. Responsibilities Packet Processing Design: Design and architect solutions for high-speed networking device, focusing on latency optimization, and quality of service (QoS) support. Prior experience with CAMs, and routing tables. Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Conduct thorough testing and validation to ensure functionality and reliability. Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics. Protocol Support: Provide support for various networking protocols and standards related to input and output queues, including Ethernet. Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including hardware engineers, firmware developers, and system architects. Qualifications ME/BE with a minimum of 8-15 years of experience. Working knowledge of system Verilog, and Verilog is Mandatory . Prior experience with ownership of memory subsystems. Proven expertise in designing and optimizing packet pipelining and QoS mechanisms, for high-speed networking devices. Solid understanding of ASIC design methodologies, including simulation, and verification tools (e.g. Synopsys, Cadence). Experience with Ethernet/PCIe networking protocols. Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues. Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences. Why Join Us? At Eridu AI, you ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. "},"

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: Team and Job Description Microchip s Data Center Solutions BU (DCS) is a leader in providing optimized semiconductor-based solutions with highly integrated software that enable the world s data center infrastructure. We are seeking a dynamic, highly technical Product Management leader to join our team. As a key member of our team, you will interact closely with customers, architects, technologists, partners and cross-functional teams to define and deliver competitive and complete silicon-based solutions. This is a unique opportunity to be in a high growth, high visibility, and high impact role driving a successful product strategy built on the most advanced silicon technologies in the world. Key Responsibilities and Expectations: This position will drive customer engagements, design wins, growth, product and business planning activities across all DCS Product Lines and Solutions with a focus on system management, performance telemetry, security, RAS Management, ease of integration and overall user experience. Responsibilities include: Define the roadmap to deliver on a differentiated and compelling vision that delivers unique and best-in-class user experience for all our products. Drive detailed collateral, tools, training, software and product features prioritized to optimally increase customer delight. Work closely with customers, applications teams and support engineering to define the proper metrices, measures, and show continues improvement of customer experience. Drive Collaboration with Microchip cross-functional teams and managing the products from concept, through the planning cycle and timely production ramp and delivery to customers. Lead across multiple product execution teams to deliver a compelling value proposition. Lead in-depth customer engagements, working closely with them on roadmap development, proof of concepts, reference designs and system level solutions. Collaborate and support go-to-market teams, sales, field support teams, marketing. Present at all levels of the organization including executives. Requirements/Qualifications: Preferred qualifications Bachelor s degree in engineering or compute science; MBA preferred 10+ years of experience in product management, product marketing, or other customer-facing product roles within the semiconductor industry. Deep understanding of Data Center infrastructure and architectures that enable Data Center Compute, Accelerated and AI. Strong background in Data Center management and security protocols like PLDM, SPDM, OpenBMC, OCP Standard, and technologies like PCIe (required), Ethernet, CXL, NVMe. Understanding of emerging Scale-up and Scale-out technologies. Strong strategic thinking with analytical skills. Experience in a similar role engaging with Hyperscale customers and large OEM s/ODM s and key ecosystem partners. Excellent communication and presentation skills, with ability to articulate complex concepts with clarity and simplicity backed up with data. Growth mindset, with focus and determination to drive impactful results. Willingness to travel as needed for customer meetings, industry events, and trade shows Travel Time: 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Apply to this job Meta is hiring ASIC Verification Engineer with in-depth understanding of PCIe Express within the Infrastructure organization. We are looking for individuals with experience in verification of PCIe Switch, Root Complex and Endpoint to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook s data center applications. You will be responsible for the verification closure of a sub-system or SoC from test-planning, Hybrid test bench development to verification closure. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC DV Engineer, PCIe Verification Responsibilities Develop and execute verification plans, test cases, and scripts to ensure PCIe interface functionality, performance, and compliance with industry standards. Collaborate with design teams to understand the PCIe interface architecture and identify potential issues. Create and maintain testbenches, including simulation models and tests Perform simulation-based testing, including functional, performance, and compliance testing Analyze test results, identify defects, and work with design teams to resolve issues. Stay up-to-date with industry trends, standards, and best practices related to PCIe verification Debug, root-cause and resolve functional failures in the design, partnering with the Design team Mentor engineers to drive and deliver high confidence verification for highly complex ASIC projects. Minimum Qualifications Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience At least 8+ years of relevant experience Track record of first-pass success in ASIC development Good knowledge of PCIe specifications, protocols, and standards covering Root Complex, End Point and Switch Good hands-on verification experience in PCIe Transaction, Link and Physical layer. Hands-on experience in Verilog, SystemVerilog, UVM , C/C++, Python based verification Experience in IP, Cluster and SoC level verification in both RTL and Gate Level Setup Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments Experience in architecting and implementing DV setup for complex Subsystem and ASICs. Experience using analytical skills to craft novel solutions to tackle industry-level complex designs Demonstrated experience with effective collaboration with cross functional teams Preferred Qualifications Experience in development of PCIe Gen6/Gen7 DV testbench and infrastructure from scratch Hands-on experience with integration and usage of varied PCIe vendor VIP Experience in performance verification of PCIe Sub-System for AI/ML Applications etc Experience with development of fully automated flows and scripts for data exploration, analysis and performance verification Experience with revision control systems like Mercurial(Hg), Git or SVN Experience with simulators and waveform debugging tools Experience working across and building relationships with cross-functional design, model and emulation teams About Meta . Equal Employment Opportunity . Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

Apply to this job Meta is hiring ASIC Verification Engineer with background in Simulation Acceleration using Emulation and Hybrid Platforms within the Infrastructure organization. We are looking for individuals with experience in Simulation Acceleration and Emulation to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook s data center applications. You will be responsible for the verification closure of a sub-system or SoC from test-planning, Hybrid test bench development to verification closure. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC DV Engineer, Simulation Acceleration and Hybrid Verification Responsibilities Propose, implement and promote the Simulation Acceleration and Hybrid Verification Methodology to be used across the group, both at the Cluster and at the SoC level Work with Architecture and Design teams to come up with functional, use case and performance test plan for the DUT Define Verification scope, create environment, testplans and close use case scenarios and performance using targeted tests at Cluster and SoC level Debug, root-cause and resolve functional failures in the design, partnering with the Design team Develop and drive continuous Hybrid Verification improvements using the latest methodologies, tools and technologies from the industry Build reusable/scalable environments for Hybrid Verification. Evaluate and recommend solutions for Hybrid Verification and Simulation Acceleration Provide training for internal teams and mentoring engineers related to Hybrid Verification Methodology Minimum Qualifications Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience At least 8+ years of relevant experience Track record of first-pass success in ASIC development Hands-on experience in Verilog, SystemVerilog, UVM, C/C++, Python based verification Experience of working with Zebu, Palladium, Veloce HW platforms Experience in Cluster and SoC level verification using Hybrid Simulation and Emulation based methodologies Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments Experience in architecting and implementing Hybrid Verification infrastructure and executing verification cycle Experience using analytical skills to craft novel solutions to tackle industry-level complex designs Demonstrated experience with effective collaboration with cross functional teams Preferred Qualifications Experience in development of Simulation Acceleration and Hybrid verification environments from scratch Experience in performance verification of complex compute blocks like CPU, GPU or HW Accelerators, Ethernet, PCIe, DDR, HBM etc Experience in verification of Data-center applications like Video, AI/ML and Networking designs or integration verification of high-speed interfaces like Ethernet PCIe, DDR, HBM Experience with development of fully automated flows and scripts for data exploration, analysis and performance verification Experience with verification of ARM/RISC-V based sub-systems or SoCs Experience with revision control systems like Mercurial(Hg), Git or SVN Experience with simulators and waveform debugging tools Experience working across and building relationships with cross-functional design, model and emulation teams About Meta . Equal Employment Opportunity . Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

Job Description We are seeking a highly skilled and experienced DFT Engineer to join our dynamic team of engineers to develop the next-generation Flash Controllers. As an SoC DFT Engineer, you will be responsible for defining and implementing industry leading DFT solutions, with emphasis on SCAN, MBIST, BSDL etc. The ideal candidate will have a deep understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG & Simulation expertise. ESSENTIAL DUTIES AND RESPONSIBILITIES: DFT Architecture definitions for SoC development Leading complex activities and providing solutions for complex DFT problems. Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs. Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies. Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs. Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology. Qualifications B.Tech / M,Tech / Phd in Electronics, Computer science or Electrical Engineering Minimum 15+ years of experience in DFT Strong understanding of DFT Architecture SKILLS : Extensive experience in SoC DFT architecture, DFT IP development and DFT methodology. Proven track record of driving DFT architecture in complex ASIC designs. Work independently on multiple complex DFT problems across different projects. Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs). Proficiency in SCAN, MBIST implementation. Solid understanding of JTAG & BSDL standards. Good understanding on Test clocking requirements, Test mode timing closure. Proficiency in complex silicon debugs and yield analysis. Solid understanding of SoC architecture and low-power design principles. Understanding of High-Speed interfaces (PCIe or UFS protocols) and experience with SSD/Flash is advantage. Excellent analytical and problem-solving skills. Strong communication skills and the ability to work effectively in cross-functional teams.

This is a great chance to create a real impact by testing NVIDIA s DriveOS automotive operating system. As a highly skilled and motivated senior software developer, you will push the boundaries of testing and automation, shaping our verification strategy and influencing the future of our test automation systems. If youre passionate about self-driving technology and ready for a challenge, we want to hear from you! What you will be doing: You will have a unique opportunity to be at the forefront of ensuring the flawless performance of NVIDIAs groundbreaking technology. Your contributions will directly impact the quality and reliability of our solutions, shaping the future of autonomous systems. In our fast-paced and dynamic environment, you will take on exciting challenges, including: Developing and refining test strategies and test plans for new features, ensuring our solutions meet the highest standards of excellence. Designing and implementing automated testing frameworks to enhance verification processes, driving efficiency and reliability in our testing pipelines. Collaborating with multi-functional teams to gain a deep understanding of customer use cases, project requirements, and feature specifications, ensuring alignment with real-world applications. Investigating, analyzing, and addressing issues found during testing, leading root-cause analysis and implementing effective solutions. Enhancing and optimizing QA processes, ensuring technical excellence while continuously improving quality standards. Providing mentorship and guidance to fellow team members, fostering a culture of collaboration, innovation, and technical excellence. Engaging with global teams across different time zones to deliver a seamless and exceptional user experience. Your expertise in testing and automation will be instrumental in shaping the success of NVIDIAs cutting-edge technology, ensuring we deliver world-class solutions to our customers. What we need to see: To excel in this role, we are looking for candidates with the following qualifications: B. E / B. Tech / MS / MCA or its equivalent degree 3+ years of relevant experience in software development Experience in using AI coding assistants to improve coding efficiency and correctness Knowledge in Linux and/or QNX is required Strong embedded testing experience Strong Python skills, with the ability to write logical scripts/code from scratch and use automation frameworks Ability to read C/C++ and low-level code Excellent analytical skills for solving problems Strong interpersonal and communication skills are important An excellent teammate demeanor, passionate about autonomous driving and related fields. Ways to stand out from the crowd: Experience in the Autonomous driving domain Proven understanding of Linux Kernel Internals, system software, Graphics, and Multimedia Concepts Proficiency in industry-standard I/Os such as Display, Resource Manager, Ethernet, CAN, PCIe, and PTP or equivalent experience LLM, GenAI Knowledge Intelligent machines powered by Artificial Intelligence computers that can learn, reason and interact with people are no longer science fiction. GPU Deep Learning has provided the foundation for machines to learn, perceive, reason and solve problems. Now, NVIDIA s GPU runs Deep Learning algorithms, simulating human intelligence, and acts as the brain of computers, robots and self-driving cars that can perceive and understand the world. Come be a part of this exciting world, at NVIDIA. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

KEY EXPERTISE Seasoned ASIC Front End leader with 20 years of cross domain experience ranging from architecture, uArch, IP/Sub- systems/SOC/ chiplets design/integration, RTL coding, Synthesis, CDC, timing, power analysis, system/IP verification, Silicon Bring up. Proven track record of leading the design and development of complex IPs, sub-systems, chiplets for SOCs in the multiple domains like PCIE, USB, UCIE, ARM/x86 CPUs, RISC-V, VPU/NPU, GPU, LSIO, NOC, Fabrics, AMBA buses, DRAM, SD/SDIO/eMMC etc. Responsible for defining the technical direction of ASIC designs and collaborating with cross- functional teams to ensure successful ASIC implementation. Demonstrated strong leadership, project timelines & resources management and team management skills, and the ability to influence the technical strategy of the organization. Familiar with ASIC verification methodologies, DFT, Physical design and board design which help in influencing cross functional teams in getting desired results. Excellent execution capabilities to handle multiple domains in multiple projects simultaneously. Delivered superior results through team collaboration and diversity of thought. Always open to learn new technologies to grow in technical breadth and depth. Managed development of multiple sub-systems and IPs designed from scratch for Intel IOT (Elkhart Lake), Edge (Reefbay), dVPU/NPU (Arrow LakeR), GPU (DMR-D), Media (MTL-D), Smart NIC (Altera NIC), Palm Ridge, Mount Morgan IPU SoCs which are executed in advanced technology nodes of both Intel (18A, 3nm, 5nm) and TSMC (N3e, N5, N6). Have hands on experience in chiplets, Sub-systems and IP development (micro-architecture development, 3rd party IP integration (Synopsys, Verisilicon. SiFive RISCV, ARM cores etc.,), RTL implementation, synthesis, static timing analysis, Power analysis, system/IP level verification, FPGA emulation, Si bring-up) and SoC integration flows and methodologies. Led 30+ engineer design team and have good experience in working with cross-functional teams and cross BU teams across multiple geos, resulting in good collaboration and accelerated time to market. Led IP development (RTL design, Lint, CDC, Synthesis, timing, unit level and system level verification) of various IPs in Nvdia Tegra SoC processors (from first generation [APX] to ninth generation [Xavier]) and Cisco NIC chips. Have good working experience on low power design methodologies (clock gating, power gating, multi-vt and DVFS) used in mobile SoCs. Designed couple of modules in Tegra SoC like DMA engine, SD/SDIO/ eMMC5.2 host controller and bus-bridges for Nvidia proprietary buses. Worked on architecture, micro architecture, RTL design and timing analysis. Familiar with automotive electronics ISO26262 safety requirements. Was Executive member from Nvidia in SD card org and JEDEC (eMMC) forum. Participated in SD/SDIO4.x, SD host4.x and eMMC5.x specification development. Working experience with cross functional teams like back end, analog I/O pad and SW teams to ensure IP requirements are met at each stage. Have working experience in developing tree build and regression infrastructure. Have hands on experience in ASIC verification also - Test Planning, Develop Directed, Random and System-level (soc level) Test Cases; Design Test Bench using System Verilog; Develop Random Test environment; Execute Code Coverage & Analyse Reports, Execute Gate-level Simulations; Execute Functional & Regression Tests. Good Team Player: Participated and lead the effort of SD4.x/eMMC5.x host controller design and verification. Detail oriented go- getter with Fast Learning Curve and strong analytical, decision making, problem solving, visualizing, negotiating, communication & interpersonal skills. Mentored engineers, designed IP/SS schedules with proper staging plan with cross team dependencies, identified and solved technical issues, and ensured development of high-quality products.

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 15 years or MSEE/CE + 12 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Work Location : Bangalore, Belgrade, Penang, New York Work Expertise : 5 - 15 years Job Specs : - Expertise in the x86 BIOS / UEFI FSP / coreboot development - Expertise with x86 CPU/APU architectures and associated compilation tools - Expertise in C programming - Expertise with platform bring-up - Expertise with standard protocols like PCIe, SPI, eSPI, ACPI, SMM - Expertise with opensource coreboot project & mainboard related porting with GPIO, PCIe lanes, board fmd configs and board bring-up experience on customer platforms. - Expertise on working with Intel FSP package source code and understanding of coreboot & FSP boot flow - Expertise with different coreboot payloads like edk2, SeaBios, Tianocore etc - Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required - Good coreboot upstreaming exposure - Familiar with coreboot boot stages, upds, memory map, FSP, devicetree concept, payloads to OS bootloader handoff - Understanding of coreboot & FSP build tools and build processes - Good understanding of UEFI framework concepts to port UEFI code to FSP - Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. - Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. - Good understanding of x86-64 architecture from BIOS developer's perspective. - Good understanding of UEFI BIOS Boot flow. - Basic understanding of Linux Kernel like software development concepts (Kconfig).

Develop testbenches, testcases, and verification components using SystemVerilog and UVM. PCIe, Ethernet, AMBA protocols must. Create and execute detailed verification plans based on design specifications Drive coverage closure, and debug failures.

Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 4-7 years of hands-on experience to the table. You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas!

Looking for Siemens EDA ambassadors Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based on? Implementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join the team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We make real what matters. This is your role. Questa verification IP"™s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don"™t need superheroes, just super minds. We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 2-4 years of hands-on experience to the table. You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas! We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare. Transform the everyday #LI-EDA #LI-Hybrid #DVT

Looking for Siemens EDA ambassadors Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based on? Implementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join the team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We make real what matters. This is your role. Questa verification IP"™s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don"™t need superheroes, just super minds. We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 1-4 years of hands-on experience to the table. You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas! We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare. Transform the everyday! #LI-EDA #LI-Hybrid #DVT

We aspire to be world-leader in innovative telecom and security solutions by offering cutting-edge, high-performance telecom and security solutions to business customers. Our Mission is simple. To prove that Indian engineers can design, develop, and manufacture world-class technology products for customers across the world, right from India. Join our team of like-minded engineers, applied researchers, and technocrats with the will, courage, and madness to achieve this mission! Why work at Matrix Matrix fully integrates software and hardware across its products. Engineers here collaborate more effectively to create solutions that solve real problems and make an impact. We are responsible for every nut, bolt, and line of code in our products! As an engineer, your involvement will be critical in the entire lifecycle of a product - right from ideation-development-production-deployment. Get to feel the sense of accomplishment that comes with creating something that solves a real and pressing problem and is used by scores of customers. About The Role Role Engineer/ Sr. Engineer - Hardware Design (Schematic) Function Hardware Design - (Schematic) Work Location Vadodara, Gujarat Who are you You are an energetic and passionate individual with extensive expertise in hardware design, particularly in schematic design. You possess a deep understanding of various hardware components and systems, including IP cameras, video recorders, access control systems, smart card readers, IP terminals, PABX, GSM gateways, military-grade cameras and recorders, and explosion-proof cameras. You thrive on tackling complex challenges and are driven by a commitment to innovation and excellence in hardware design. Experience 1 - 5 Years (Freshers can also apply) Qualification B .E/ B.tech/ M.E/ M.tech (EC, Electronics & Communication) OR MSc (EC/Electronics) Technical Skills Required : Experience on all stages of Hardware Product Development Lifecycle. Development of high speed board design in embedded domain. Should have hands-on experience of Schematic design. Experience on all stages of the Hardware Product Development Lifecycle. Designing and developing components such as printed circuit boards (PCB), processors, memory modules, and network components. Experience on High-Speed Interfaces like DDR, Memory, Audio, USB, Ethernet (Experience on HDMI, SATA, MIPI, CSI, USB, I2C, SPI will be additional benefit). Working experience in hardware design of Micro-ProcessorsTI, ARM CORTEX A7/A9, Freescale, NXP, Qualcomm. MemoriesDDR2, DDR3, LPDDR2/3. EMI-EMC Compliance related basic knowledge. Exposure of Design testing. Deriving H/W design requirements from EMI, EMC, Safety & Automotive EMC/Transients test standards. Preparing BOM (Bill of material) in the most efficient way. Thermal and product reliability know how. Alternate part approval and verification (Electronics components characteristics know how). How your day might look like Design block diagram and architecture for product design Create schematic diagrams following engineering layout principles and industry standards Evaluate and prepare comparison of parts Review and revise schematic designs to ensure accuracy, functionality, and alignment with project requirements. Secure approvals for component selections and design decisions from stakeholders Integration with other engineering departments for product definition (System design, Schematic and Layout integration, upfront work with vendor team). Oversee design and testing related management with structural workflow. Product certification support like CE, FCC and other safety standards Work on high-speed interfaces such as RGMII, MIPI-DSI, PCIe Gen3, MIPI-CSI, eMMC, and USB 3.0 to ensure seamless integration and performance. What we offer Opportunity to work for an Indian Tech Company creating incredible products for the world, right from India Be part of a challenging, encouraging, and rewarding environment to do the best work of your life Competitive salary and other benefits Generous leave schedule of 21 days in addition to 9 public holidays, including holiday adjustments to convert weekends into long weekends 5-day workweek with 8 flexi-days months, allowing you to take care of responsibilities at home and work Company-paid Medical Insurance for the whole family (Employee+Spouse+Kids+Parents). Company paid Accident Insurance for the Employee On-premise meals, subsidized by the company If you are an Innovative Tech-savvy individual, Look no further. Click on Apply and we will reach out to you soon!

locationsIndia, Bangaloreposted onPosted Today job requisition idJR0275251 Job Details: About The Role : Intel is at the forefront of the wireless communication industry, offering cutting-edge products that set the standard for performance and innovation. We are seeking a highly skilled SerDes PHY System Engineer to join our team. In this pivotal role, you will be responsible for the design and development of physical layer components for high-speed SerDes systems, ensuring their performance and reliability. Key Responsibilities: SerDes PHY DesignLead the design and development of the physical layer for SerDes systems, including transmitter and receiver architectures, equalization techniques, and signal integrity. Simulation and ValidationConduct comprehensive simulations using MATLAB and Python, along with lab testing, to validate the performance and compliance of the SerDes PHY, optimizing it for high-speed data transmission. Calibration TechniquesDevelop and implement calibration methods to enhance the performance of the SerDes PHY, ensuring high-quality data transmission. CollaborationWork closely with cross-functional teams, including digital design, hardware, and software, to ensure seamless integration of the PHY layer into the overall SerDes system. DocumentationMaintain detailed and up-to-date documentation of design specifications, test plans, and results. Problem-SolvingAddress and resolve complex technical issues related to the SerDes PHY, ensuring optimal performance. Quality AssuranceImplement quality control measures and best practices to ensure the reliability and robustness of the SerDes PHY. Qualifications: Bachelor's degree in Electrical Engineering; a Master's degree in a relevant field is preferred. Minimum of 5 years of experience in wired or wireless communication systems. Proven experience and enthusiasm for lab work, collaboration, and solution development. Prior experience in DDR/PCI/GDDR7/UCI will be added advantage. Proficiency in scripting and programming languages such as C, C#, MATLAB, and Python. Experience in silicon development and SerDes technologies is advantageous. Strong problem-solving abilities and analytical skills. Self-motivated and capable of executing tasks in uncertain environments. Demonstrated leadership skills and ability to drive initiatives in a matrix organization. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries ofscience and engineering to make possiblethe next generations of technology, join us to Make Possible a Better Future. What We Offer Location: Bangalore,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. We're committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our . You'll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers.We empower our team to push the boundaries of what is possible"while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. HARDWARE DESIGN AND SUPPORT ENGINEER About Applied Applied Materials is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations make possible the technology shaping the future. Our Team Your O pportunity As a hardware Support Engineer, you can deepen your technical skills and become an expert in specific technologies or equipment. This expertise can lead to roles where you might take on more complex projects and responsibilities. Roles and Responsibility Understand specifications and schematics for image computers, ensuring compatibility with other hardware and software systems. Integrate image processing hardware with existing systems, ensuring seamless operation and high performance. Develop testing protocols for image computers and system controllers to validate functionality and performance. Conduct rigorous testing and analysis to identify and resolve issues in hardware design and integration. Provide technical support for image computers and system controllers, diagnosing and resolving hardware and integration issues. Collaborate with software and firmware engineers to troubleshoot system-level problems and optimize performance. Maintain documentation for all hardware designs, integration processes, and troubleshooting efforts. Communicate effectively with stakeholders to gather requirements, provide updates, and deliver technical support. Our Ideal Candidate Handling the SFP, SFP+ QSFP module for Network management Working as lab POC for all lab management and project execution activities and the status report of the lab handling. Proficiency in hardware testing and validation techniques. Excellent problem-solving skills and attention to detail. Strong communication skills and ability to work collaboratively in a team environment. Familiar with server architectures, specs, roadmaps, cost vs. performance. Including CPUs, PCIe, GPUs, memory, interconnects, networking, power, cooling, SW interfacing. Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering/ECE/EEE, or a related field. Additional Qualifications: Understanding of laboratory environments and the specific requirements for testing and development within such settings. Ability to manage multiple projects and adapt to changing priorities and technologies. Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 15 years or MSEE/CE + 12 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Mandatory Skills: 1. Engineer with 5+ years of experience in Windows driver framework. 2. Strong C/C++ development skills with a good understanding of object-oriented design. 3. Good debugging skills, knowledge in using debug tools like WinDbg and BSOD analysis. 4. Good knowledge in OS internals, x86/ARM System architecture and system buses like PCIE/SATA/USB/I2C/SPI & I/O Subsystems. 5. Strong background in embedded systems development and bringup. 6. Experience with low-level hardware device programming 7. Experience with Multimedia & Graphics architecture. Good to have: Understanding of different Windows OS versions. Knowledge in Linux development Good written and verbal communication skills. Self-motivated, should be able to take lead in mastering new technologies. Should be able to work as an individual or team member.

In this role, you will work on SoC/Sub-system level prototype development and design bring-up on HAPS/Pro FPGA HW platforms. Additionally, you will work closely with design, verification, validation, and SW teams to implement emulation testbench and features required to develop content on prototyping models. You would be required to develop/port tests to qualify models. Key Skills 8-15 years of experience on SoC/Sub-system prototyping of multi-million gate and complex design with multiple clocks and power domains Experience in microcontroller architecture, Cores ARM A/M series, Interconnect (NIC, FlexNoC), Protocols like AHB, AXI, Memory (Flash, SRAM, DDR4/5), and memory controllers Experience in automotive protocols like LIN, CAN, high-speed protocols like PCIe, Ethernet, USB, etc. would be an advantage Prototyping model development with actual target HW Experienced in HAPS/Pro FPGA prototyping platforms Create and execute test plans targeting model qualification Experience with Speed Bridge Integration and performing real-time testing would be a plus Scripting and automation to continuously improve operational efficiency

In this role you will work on SoC/Sub-system level Emulation model development and design bring up on Zebu/Veloce HW platforms. Additionally, you will work closely with design, verification, validation, and SW teams to implement emulation testbench (XTORs, Speed Adaptors) and features required to develop content on emulation models. You would develop tests to qualify models. Key Skills 8-15 years of experience on SoC/Sub-system Emulation of multi-million gate and complex design with multiple clocks and power domains Experience in microcontroller architecture, Cores ARM A/M series, Interconnect (NIC, FlexNoC), Protocols like AHB, AXI, Memory (Flash, SRAM, DDR4/5), and memory controllers Experience in automotive protocols like LIN, CAN, high-speed protocols like PCIe, Ethernet, USB etc. would be an advantage Emulation model creation from RTL/Netlist Experienced in Zebu/Veloce emulation platforms Create and execute test plans targeting emulation model qualification Experience with Speed Bridge Integration and perform real-time testing would be a plus Experience in integrating Acceleration VIPs/XTORs and perform co-emulation Scripting and Automation to continuously improve operational efficiency.

We are seeking an exceptional Senior ASIC Verification Engineer to join our innovative semiconductor team. You will lead verification initiatives for complex ASIC designs and drive technical excellence across projects. About the Role : You will be responsible for developing advanced verification environments, leading cross-functional technical initiatives, and mentoring team members while ensuring the highest quality standards in our ASIC designs. What You'll Do : - Design and implement advanced System Verilog/UVM verification infrastructures - Lead verification planning and execution for complex ASIC projects - Develop comprehensive test strategies ensuring thorough design validation - Drive debug resolution through collaboration with cross-functional teams - Mentor and provide technical guidance to verification team members - Enhance and optimize verification methodologies - Own end-to-end SOC verification environments Required Skills & Experience : - BS/MS in Electrical/Computer Engineering - 2+ years of hands-on ASIC verification experience - Expert-level SystemVerilog, UVM, and object-oriented programming skills - Strong proficiency with industry tools like VCS, Xcelium, QuestaSim - Advanced debugging and problem-solving capabilities - Excellent communication and collaboration abilities - CLP and GLS - Python/Perl scripting expertise Nice to Have : - Experience with PCIe, DDR, USB, C2C - Knowledge of on-chip interconnects and processor subsystems - Background in formal verification methods - Prior experience on Emulators