665 Pcie Jobs - Page 6

Experience Level: Over 4 years Location: Bangalore Skills: Proficiency in SystemC, C++, and SV/Verilog, coupled with hands-on coding experience in these languages. Strong aptitude for debugging and effective communication. Familiarity with scripting languages (desirable). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

We are seeking a highly skilled and experienced Lead Verification Engineer with expertise in USB/LPDDR and a strong knowledge of Cadence VIP. The ideal candidate will have a deep understanding of low-power design and verification techniques. Responsibilities: Develop and execute comprehensive verification strategies for USB/LPDDR subsystem designs, considering low-power design requirements. Collaborate with cross-functional teams to define verification goals and ensure alignment with project objectives. Design and implement reusable, scalable, and efficient verification testbenches using SystemVerilog/UVM or C based . Leverage Cadence VIP and other verification IPs to accelerate the verification process. Low-Power Design VerificationApply expertise in low-power design and verification techniques to ensure accurate and reliable verification of power management features, including power states, power domains, and power-aware verification methodologies. : Extensive experience (8+ years) in verification. Strong knowledge of Cadence VIP and verification methodologies (SystemVerilog/UVM). Proficiency in low-power design techniques and power-aware verification methodologies. Hands-on experience with industry-standard simulation and verification tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Questa). Solid understanding of verification languages (SystemVerilog, VHDL) and scripting languages (Perl, Python, TCL). Familiarity with industry standards and protocols related to USB (USB 2.0, USB 3.x) and LPDDR (LPDDR4, LPDDR5). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

We are seeking a skilled and motivated DDR5/SerDes Verification Engineer to join our organization. As a DDR5/SerDes Verification Engineer, you will be responsible for verifying and validating the functionality and performance of DDR5 memory subsystems and high-speed SerDes interfaces. In addition to strong DDR5 and SerDes verification expertise, knowledge and experience with sideband I2C and I3C protocols would be considered a plus. Candidate should have Design and implement advanced verification environments and test benches using SystemVerilog/UVM Experience4-10 Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience Level: 8+ years Location: Bangalore/Hyderabad Skills: Profound expertise in MACSec and Ethernet technologies. MACSec (Media Access Control Security): Proficient in point-to-point security implementation on Ethernet links, adhering to the IEEE 802.1AE-2018 standard. IPsec (Internet Protocol Security): Skilled in establishing security between two devices across an Internet Protocol network. Hands-On Knowledge: Proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), with practical experience in their application. Testbench Development: Demonstrated experience in developing comprehensive Test Benches (TB) and individual verification components. Communication and Leadership: Possesses excellent communication skills and adept at leading and coordinating teams effectively. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification and possess a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). This role specifically requires expertise in GLS (Gate-Level Simulation). Key Responsibilities: IP and SOC Verification Conduct IP and SOC verification activities to ensure the functionality and correctness of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate strong knowledge of SystemVerilog and Universal Verification Methodology for efficient and effective verification processes. Gate-Level Simulation (GLS) Proficiency in Gate-Level Simulation is a mandatory requirement for this position. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM). Proficiency in Gate-Level Simulation (GLS). If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of integrated circuits, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly experienced Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong foundation in SystemVerilog (SV) and Universal Verification Methodology (UVM). In addition to standard verification skills, this role requires expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST (Memory Built-In Self-Test), SCAN, PG (Pattern Generator), and PM (Pattern Memory). Key Responsibilities: IP and SOC Verification Perform comprehensive IP and SOC verification to ensure the reliability and functionality of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate a strong understanding of SystemVerilog and Universal Verification Methodology for efficient verification processes. CDP, GDP, DFT DV Expertise Possess expertise in Compressed Data Pattern (CDP) and Generic Data Pattern (GDP) methodologies. Proficiency in Design for Test in Design Verification (DFT DV) techniques, including JTAG, MBIST, SCAN, PG, and PM. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong knowledge of SystemVerilog (SV) and Universal Verification Methodology (UVM). Expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST, SCAN, PG, and PM. If you are a talented Design Verification Engineer with a deep understanding of IP and SOC verification, as well as specialized expertise in CDP, GDP, and DFT DV methodologies, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Number of Open Positions: 7 Location: Bangalore Experience: 4 to 7+ years : We are currently seeking talented and experienced Design Verification Engineers to join our team in Bangalore. As a Design Verification Engineer, you will be responsible for ensuring the functionality, performance, and reliability of our complex designs, with a focus on Core Data Path (CDP), Graphics Data Path (GDP), USB4 (USB 4.0), Power Gating (PG), and Power Management (PM) domains. We are looking for candidates with 4 to 7+ years of relevant experience in design verification. Key Responsibilities: Verification Planning: Collaborate with design and architecture teams to develop comprehensive verification plans for CDP, GDP, USB4, PG, and PM components. Testbench Development: Create and maintain advanced testbenches, including constrained-random and assertion-based methodologies, to thoroughly verify design functionality. Functional and Coverage Testing: Execute functional tests and track coverage metrics to ensure exhaustive testing of design features. Protocol Verification: Verify compliance with industry-standard protocols, including USB4, and identify and address protocol violations. Bug Reporting and Debugging: Document and report issues, and work closely with design teams to resolve bugs in a timely manner. Performance Verification: Assess and verify the performance of data path components, ensuring they meet specified requirements. Power Verification: Verify power management and power gating strategies to optimize power consumption. Scripting and Automation: Develop and use scripting languages and automation tools to streamline verification processes. Documentation: Prepare detailed verification plans, test reports, and documentation. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field. 4 to 7+ years of experience in design verification. Strong knowledge of CDP, GDP, USB4, PG, and PM domains. Experience with industry-standard verification methodologies and tools. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. If you are a highly motivated and detail-oriented Design Verification Engineer with a passion for ensuring the quality and reliability of complex designs, we encourage you to apply. Join our team to work on cutting-edge technologies and contribute to the success of our projects. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Take the lead in advanced design verification!Were looking for a Senior Design Verification Engineer in Bangalore to work onHBM, DDR, UCIe, PCIe protocols, and more.Key Skills: System Verilog/UVM, protocol verificationExperience Required3+ YearsJoin our team and help shape groundbreaking designs. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Number of Open Positions4 Experience: 4+ years Location Hyderabad : We are looking for a highly skilled and experienced Gate-Level Simulation Engineer to join our team. The ideal candidate should have a minimum of 4 years of experience and possess a strong background in gate-level simulation (GLS). Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM) is essential for this role. Key Responsibilities: Collaborate with cross-functional teams to define and execute gate-level simulation test plans. Develop and implement gate-level simulation strategies for complex digital designs. Conduct gate-level simulations to verify the functionality and performance of digital designs. Work closely with design and verification teams to identify and resolve issues at the gate level. Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process. Ensure compliance with industry standards and best practices in gate-level simulation. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 4+ years of experience in gate-level simulation. Strong proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). Prior experience in gate-level simulation is essential. Familiarity with gate-level simulation tools and methodologies. Excellent problem-solving skills and attention to detail. Effective communication and collaboration skills. Ability to work in a dynamic and fast-paced environment. If you are a motivated and experienced Gate-Level Simulation Engineer with a strong background in SV, UVM, and a passion for ensuring the quality and reliability of digital designs at the gate level, we encourage you to apply for this position. Join our team and contribute to the success of our cutting-edge projects. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaHyderabad

Let your ideas power the next wave of technology!Were hiring Design Verification Engineers for Bangalore and Hyderabad.Experience Required4"“18 YearsKey Skills: HSIO protocols like PCIe, DDR5, HBM, USB, low-power simulationsWork on cutting-edge verification projects and take your career to new heights. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Design Verification Engineer (5-7 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Design Verification Engineer (7-10 years’ experience) Company: HCL Tech Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement Design Verification Engineer (Senior Level - 10+ years’ experience) Company: HCL Tech Job Summary: We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies. Responsibilities: Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification) Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team Champion best practices for verification code quality and participate in code reviews Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies Provide technical leadership and contribute to the overall verification roadmap for the team Qualifications: Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred) Minimum of 10+ years of experience in Design Verification for complex ASICs and SoCs Proven track record of successfully leading and executing verification projects In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages) Excellent leadership, communication, collaboration, and problem-solving skills Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines Benefits: Competitive salary and benefits package commensurate with experience and expertise Opportunity to lead and influence the verification of cutting-edge technologies Dynamic and challenging work environment with opportunities for professional growth and leadership development Recognition and rewards for outstanding contributions

Job Overview: We are seeking an experienced and detail-oriented PCIe Protocol Engineer to work on high-performance hardware systems involving PCI Express (PCIe) architecture. The role involves protocol development, validation, and debugging at the IP or SoC level, contributing to next-generation computing and storage solutions. Key Responsibilities: Develop, verify, and validate PCIe protocol layers (L1, L2, L3) in compliance with PCIe standards. Design and implement testbenches, monitor signal integrity, and debug PCIe-related issues. Work on IP/SoC integration and validation of PCIe controllers and PHYs. Collaborate with cross-functional teams including hardware, firmware, and verification teams. Analyze protocol traces (e.g., using tools like Teledyne LeCroy, Synopsys Verdi) to ensure functionality. Ensure compliance with PCIe Gen3/Gen4/Gen5/Gen6 specifications and interoperability requirements. Location- Remote, Delhi NCR, Bengaluru, Chennai, Pune, Kolkata, Ahmedabad, Mumbai, Hyderabad

You have an exciting opportunity to join TekWissen as a BIOS - UEFI - Coreboot professional in Bangalore. As a part of our global workforce management team, you will play a crucial role in x86 coreboot/FSP/BIOS development. We are looking for individuals with 5-15 years of experience who are experts in C language and have a strong understanding of x86 CPU/APU architectures. Your responsibilities will include working on platform bring-up, industry standard protocols like PCIe, SPI, eSPI, ACPI, SMM, and collaborating with the open-source coreboot project. You will also be involved in mainboard related porting with GPIO, PCIe lanes, board fmd configs, and board bring-up experience on customer platforms. In addition to your technical skills, knowledge of Intel FSP package source code, coreboot & FSP boot flow, UEFI framework concepts, and the ability to read platform Hardware and Processor specifications are essential for this role. You should also have working knowledge of Git for code reviews, source code management, and BIOS releases to QA. Having a Bachelors degree in computer science engineering is a minimum requirement, and a Masters degree from a reputed university would be a significant advantage. As an equal opportunity employer, TekWissen Group values workforce diversity and encourages individuals from all backgrounds to apply. If you are a proactive professional with a passion for BIOS development and a solid understanding of x86-64 architecture and UEFI BIOS Boot flow, we would love to hear from you. Join us in shaping the future of technology and make a difference in the global workforce management industry.,

We are hiring PCIe engineers: -In-depth knowledge and experience with PCIe protocols upto Gen5 -Good experience of system Verilog -handson experience of working on UVM -Good to have scripting language Perl/Shell/python

1.DV 2.PD 3.DFT 4.RTL 5.PD(VLCP)/(EMIR) 6.PV 7.STA/Synthesis

: Strong knowledge in SIPI fundamentals i.e. IL, RL, Xtalk, Zpdn/Ztargets, TDR and SIPI debugging skills Must be aware of design techniques used to compensate channel losses for HS interfaces Proficiency in creating and simulating systems using IBIS/IBIS-AMI, CPM, HSPICE/Netlist and S-parameter models Can drive the system timing budget and influence hardware and IO design for higher toggle speed and BW Evaluate the impact of channel loss, reflection, crosstalk, and supply noise on overall system performance Expert in package and PCB extraction tools (PowerSi, Sigrity, Hyperlynx, Ansys HFSS/SiWave) Knowledge of package/PCB stack-up design and layout improvement techniques Experience in decoupling capacitor placement and its optimization to improve Zpdn Hands-on experience in ADS to run transient and frequency domain analysis Demonstrate familiarity with various High-Speed interfaces such as PCIE, USB, UFS, SATA, DDR, LPDDR, GDDR, HBM, NAND etc Others : Strong technical, written, and verbal skills required to prepare/present his/her own work independently to the internal/external customers Ability to drive initiatives through innovation, handle discussions with all stakeholders, take data driven decision, and meet deadlines with their own Automation & scripting(Python, Perl) knowledge is a plus Qualifications Bachelors, Master s or PhD in relevant field 5-12 years of experience in Signal and Power Integrity domain

Role : ASIC RTL Engineer / Digital Design Location . pan India or Onsite. SoC subsystem/IP design, RTL quality checks (Lint, CDC) If you interested so please share your updated cv at sugrabano@praxists.co.in - 9582126775

We don't need Linux Administrator C proram,Linux Device Driver,Kernel Module Development,Linux Kernel & User Space program,Device Driver Development,Linux Device Model,Driver Framework,X86 Multi-Core Processor,Shell Scripting,Makefiles,PCIe, Ethernet

The position requires 2-6 years of experience with micro architecture design and system design using Verilog, SV, or VHDL. You should also have experience in Spyglass Lint, CDC, SoC Integration, logic design with Verilog and SV, ASIC Synthesis, STA, timing closure, and working with any Processor based system. Familiarity with design using SoC, AXI/AHB/APB System bus, and peripherals such as Ethernet, PCIe, DDR, USB, UART, SPI, and I2C is essential. You will be responsible for synthesis, timing analysis using various industry standard tools, and should have proficiency in TCL and Python scripting. The ideal candidate for this role should have a notice period of immediate availability to 1 month. The position is based in BLR/Hyd locations.,

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation to create a smarter, connected future for all. As a Qualcomm Software Engineer, your role will involve designing, developing, creating, modifying, and validating embedded and cloud edge software, applications, and specialized utility programs. Through this, you will contribute to launching cutting-edge, world-class products that not only meet but exceed customer needs. Collaboration with systems, hardware, architecture, test engineers, and other teams is essential to design system-level software solutions and gather information on performance requirements and interfaces. The ideal candidate for this position should hold a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field. Additionally, having 1 to 2 years of experience with embedded systems, knowledge and experience in device driver development, firmware development, good analytical and problem-solving skills, proficiency in C/C++, understanding of microprocessor and multiprocessor architecture, and excellence in basic real-time/embedded programming concepts are required. Experience in peripheral interface drivers such as USB, PCIe, I2C, SPI, UART, and ACPI/UEFI would be considered a plus. Qualcomm is an equal opportunity employer that is committed to providing accessible processes for individuals with disabilities. If accommodation is needed during the application/hiring process, individuals can reach out to disability-accommodations@qualcomm.com or Qualcomm's toll-free number for support. Qualcomm also expects its employees to comply with all applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is exclusively for individuals seeking employment at Qualcomm. Staffing and recruiting agencies, as well as individuals being represented by an agency, are not authorized to submit profiles, applications, or resumes through the site. Unsolicited submissions from agencies will not be accepted, and Qualcomm will not respond to requests for updates on applications or resume inquiries. For more information about this role, please contact Qualcomm Careers.,

You are an experienced and highly skilled Senior SOC Design Verification Engineer with over 10 years of experience, specializing in PCIE (Peripheral Component Interconnect Express) protocols. As a key member of the team at Eximietas Design, you will be responsible for ensuring the robustness and correctness of cutting-edge System on Chip (SoC) designs. Your role will involve developing and implementing verification plans for complex SoC designs, with a particular focus on PCIE subsystems. You will work on creating and maintaining advanced testbenches using SystemVerilog and UVM (Universal Verification Methodology), as well as writing and executing test cases to verify functional and performance requirements, especially for PCIE protocols. Your responsibilities will also include debugging and resolving functional and performance issues in collaboration with design and architecture teams, developing and enhancing verification environments for PCIE and related interfaces, performing coverage-driven verification, and ensuring coverage closure. You will collaborate with cross-functional teams to define verification strategies and methodologies, mentor junior engineers, and contribute to the continuous improvement of verification processes. To qualify for this role, you should have a strong background in SoC design verification, with expertise in SystemVerilog, UVM, and PCIE specifications (e.g., PCIE Gen3/Gen4/Gen5) and verification methodologies. You should be proficient in developing and debugging complex testbenches and test cases for PCIE subsystems, with experience in coverage-driven verification and achieving coverage closure. Familiarity with AMBA protocols (AXI, AHB, APB), low-power verification techniques, power-aware simulation, and formal verification tools and methodologies will be beneficial. Strong problem-solving skills, attention to detail, excellent communication, and teamwork skills are essential for this role. Preferred skills for this position include knowledge of scripting languages like Python, Perl, or Tcl, familiarity with machine learning accelerators or AI/ML-based SoC designs, and experience with advanced process nodes (e.g., 7nm, 5nm). In return, Eximietas Design offers you the opportunity to work on cutting-edge SoC designs and innovative technologies in a collaborative and inclusive work environment. You will receive a competitive compensation and benefits package, along with professional growth and development opportunities.,

THE ROLE: The focus of this role in the AECG ASIC organization is to play a key role in driving project success across architecture, design, verification, and physical design. You ll collaborate with cross-functional teams, tackle different problems with diligence for next generation ASICs that meet Engineering, Business and Customer requirements with best PPA. THE PERSON: The ideal candidate will have a strong interest in Architecture, Digital Logic Design and Verification, Design for Test, Synthesis, Static Timing Analysis, Power Verification and optimization, Physical Design aspects like Floorplan, Full chip timing, Place and Route and Utilization experiments. While we do understand that it is very difficult to have knowledge on expected areas, the candidate should have strong foundation in digital design to pick up the necessary concepts and should strive to continuously learn on the job. Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or any pre-silicon technical issue. You should be able strike a balance between collaborative problem-solving and independent solution development. KEY RESPONSIBILITIES: Study both high-level and micro-architecture specifications to gain an in-depth understanding of new features or changes proposed in new projects. Developing micro-architecture specifications and refining execution methodologies for cutting-edge chip designs. Work with Architecture/RTL/DFT teams for having optimal design. Technical lead on AECG ASIC solutions, tackling problems across domains with focus on driving the best Power, Performance, Area with quality silicon for customers. Manage and monitor changes in the given tasks as project matures and be quick to re-align with new or different requirements. Work with customers and internal teams to evaluate IP choices, analyze die size and provide floorplan tradeoffs during customer acquisition phase. Work with technology/PD teams to drive signoff margins, reliability related analysis for ASIC use cases. Develop technical relationships with broader AMD Design/CAD community and peers. PREFERRED EXPERIENCE: Strong understanding of development of custom ASICs for external customers. Ability to co-optimize and make appropriate tradeoff across architecture, front-end design, and back-end design. Strong understanding of SoC Architecture and Digital Design concepts. Strong background in STA, Clocks and Power optimization techniques. Experience with Verilog or SystemVerilog and UVM Knowledge of power management, boot, CPU, AXI Interconnect and I/O peripherals Knowledge of PCIE, JESD, CPRI Understanding in physical design for PPA optimization. Proven track record of delivering SOCs in process technologies 7nm and below. Experience in leading a small team of high performing individuals. EDUCATION & EXPERIENCE: Bachelors or Masters degree in in Electrical Engineering or Computer Science. 15+years of experience in ASIC development. LOCATION: Bangalore #LI-RP1

Responsibilities As a creative design engineer with a knowledge of subsystems and SoCs you will be part team developing Subsystems & SoCs. You will work with Architects to capture the requirements and develop Micro-architecture specifications for one or more SOC areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc. Key responsibilities will include writing micro-architecture and work with Design team to deliver high quality RTL. Collaborate with verification and Validation team to review test plans, and help debug design issues. Closely work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA. Contribute to developing and improving the design methodologies. Guide and support other members of the team for overall Program success. Balance other opportunities such as working with Project Management on activities, plans, and schedules Required Skills and Experience: Bachelors or Master s degree or equivalent experience in Electronics/Electrical Engineering. Experience of 8+ years working in design of complex compute subsystems or SoCs Expertise in developing Micro-architecture and Design specifications for the SoC Infrastructure areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc. Solid understanding of digital hardware design and Verilog HDL. Experience in development and Tapeout of Complex SoC and RTL Development. Experience leading and developing RTL for Subsystems or SoCs. Conversant with Lint, CDC and RDC flows. Good communication (written, verbal, presentations) skills. Experience with Perl, Python or other scripting language Desired Skills and Experience: Experience with ARM-based designs and/or ARM System Architectures Experience developing subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet Experience with SystemVerilog and verification methodologies UVM/OVM Experience leading small teams or projects Experience or knowledge in the following areas Synthesis and timing analysis Static design checks, including CDC, RDC, X-Propagation, Linting Power management techniques DFT and physical implementation Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arm s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm

Hiring Design Verification Engineers for Bangalore location. Exp: 5+ Years Company: Eximietas Design Job Area: Engineering Group, Engineering Group > Hardware Engineering. Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. Our success is anchored in the unparalleled expertise of our engineering leadership team, whose collective experience spans renowned tech giants like Google, Cisco, Microsoft, Oracle, Uber, Broadcom, and Sun. With a commitment to innovation and excellence, we deliver cutting edge solutions that empower businesses to thrive in the ever-evolving digital landscape. Minimum Qualifications: 5+ years of Design verification experience. Strong understanding of design concepts and ASIC flow Prior work experience on IP, Subsystem and Soc verification. Strong SV/UVM coding skills. Strong understanding of RAL Hands-on experience on third party VIP Integration. Strong solving , analytical and debugging skills. Strong understanding of AMBA protocols like generic AXI, APB, AHB Hands on verification experience in Low speed peripherals like, I2C, SPI, QSPI, DMA, Interrupt controller, GPIO, UART Hands on verification experience in any of the high-speed protocol like PCIE, CXL, Ethernet or USB Hands on experience in any of the memory protocols like DDR, LPDDR or HBM Hand on experience with verification tools such as VCS, Xcelium, Waveform analyzer and third-party VIP integration. Hands on experience with revision control flow like Git, SVN, Perforce Hands on experience withGLS and Power aware simulation (UPF) Experience in a team lead role, including guiding and mentoring team members, and ensuring effective collaboration and communication within the team. As a Senior verification engineer candidate will be responsible to work at IP, Subsystem or SoC verification related tasks. Responsibilities: Develop testbench components (Driver, Monitor, Scoreboard) from scratch or enhance an existing testbench for a given IP, Subsystem, or SOC. Understand design specifications and implementation to define the verification strategy. Create testbench micro-architecture, test plan, and coverage plan documents. Define the verification scope, develop test plans and tests, and establish the verification infrastructure to ensure design correctness. Implement SystemVerilog assertions and functional coverage. Analyze code coverage and address missing scenarios to meet coverage goals. Work with other verification team members to develop, execute, and analyze verification test cases and sequences, providing relevant solutions to issues. Collaborate with architects, designers, and pre- and post-silicon verification teams to meet deadlines. Coordinate with customer leads, ensuring all deliverables and timelines are met. Serve as the project's point of contact, responsible for verification signoff.

The ideal candidate for this position at Qualcomm India Private Limited will utilize their knowledge and experience to offer leadership, technical guidance, and execute silicon validation of ARM or DSP based multiple SOC projects and platforms. The candidate should possess a strong understanding of digital design and SOC architecture, along with a good grasp of Object-Oriented Programming (OOP) concepts. Experience in Hardware Verification Languages (HVL) such as System Verilog, UVM/OVM, and System C, as well as Hardware Description Languages (HDL) like Verilog is required. Knowledge of ARM/DSP CPU architecture and High-Speed Peripherals such as USB2/3, PCIE, or Audio/Multimedia is essential. Additionally, familiarity with Power-aware Verification, GLS, Test vector generation, and Version managers like Clearcase/perforce is advantageous. Proficiency in scripting languages like Perl, Tcl, or Python is preferred. The candidate should possess strong analytical and debugging skills. Experience in Hifi Processor, Soundwire interface, ANC, DMA, I2S verification is considered a plus. Qualcomm is looking for candidates who hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of Hardware Engineering or related work experience. Alternatively, candidates with a Master's degree in the mentioned fields and 5+ years of relevant experience, or a PhD with 4+ years of relevant work experience are encouraged to apply. A total of 12-15 years of experience with a Bachelor's/Master's degree in Electrical/Electronics engineering is also acceptable. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities during the application/hiring process. Interested candidates are encouraged to reach out for accommodations if needed. Qualcomm expects its employees to comply with all relevant policies and procedures, including those related to security and the protection of confidential information. Please note that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies, as well as individuals being represented by an agency, are not permitted to use this site for submissions. Qualcomm does not accept unsolicited resumes or applications from agencies. For further information about this role, please contact Qualcomm Careers directly.,