www.Sevyamultimedia.com Verification Design Manager / Senior Manager About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Our embedded design services are centered around FW validation & Test Automation Chip Design Services Analog IP Design Foundation - OpAmp, Bandgap IOs - GPIO, I2C, LVDS Clocking - PLL Power - LDO SoC Design RTL Design, Integration, Lint/CDC/RDC, UPF IP/SoC UVM Verification PPA, Synthesis, Constraints Management Physical Design, Timing Closure, ECOs Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC PDK, Design Automation DRC/LVS/Extraction Rule deck Development PCell Development Automation Tools in Perl, Python, GoLang Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia ================ Design Verification Manager / Lead ### Job Description: Design Verification Manager / Lead DV lead/manager to verify IP/SoC using System Verilog / UVM --------------------------------------------------------------------------------------- Exposure to various interface IP like I2C/SPI/UART/USB/NVM/PCIe; Buses AXI/AHB/APB; ARM based SoC designs is needed. Skills: Overall 10+ years industry experience with 5+ years in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC verification using advanced technologies. Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator). Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

www.Sevyamultimedia.com Verification Design Manager / Senior Manager About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Our embedded design services are centered around FW validation & Test Automation Chip Design Services Analog IP Design Foundation - OpAmp, Bandgap IOs - GPIO, I2C, LVDS Clocking - PLL Power - LDO SoC Design RTL Design, Integration, Lint/CDC/RDC, UPF IP/SoC UVM Verification PPA, Synthesis, Constraints Management Physical Design, Timing Closure, ECOs Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC PDK, Design Automation DRC/LVS/Extraction Rule deck Development PCell Development Automation Tools in Perl, Python, GoLang Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia ================ Design Verification Manager / Lead ### Job Description: Design Verification Manager / Lead DV lead/manager to verify IP/SoC using System Verilog / UVM --------------------------------------------------------------------------------------- Exposure to various interface IP like I2C/SPI/UART/USB/NVM/PCIe; Buses AXI/AHB/APB; ARM based SoC designs is needed. Skills: Overall 10+ years industry experience with 5+ years in Design Verification using System-Verilog/C/UVM. Generic knowhow on Digital Design and Verification methodologies. Experience in System Verilog/UVM based IP/SoC verification using advanced technologies. Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator). Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon RTL Design Engineer :- • Job Description o As a member of Design(RTL) team, you will be responsible for the microarchitecture and design of IPs/Controllers for SoC/SiP designs. o Perform architectural/design trade-offs for required product features, performance and system constraints. o Responsible for defining and documenting design specifications. o Develop and deliver a fully verified RTL to achieve the design targets and quality sign-off requirements. o Design and Implement logic functions that enable efficient test and debug. o Provide Debug support for design verification and post-silicon activities. • Skill and Experience Requirements: o Minimum 7 + years industry experience with Masters degree (preferred) or Bachelors degree in Electrical or Computer Engineering. o Hand-on experience with micro-architecture and RTL development (System Verilog) for x86/ARM CPU Processors or high-speed custom ASICs/Accelerators with focus on any one: Cache controller, IO interfaces (PCIe, CXL, Ethernet), UCIe, Memory controllers, Display, Video encoding/transcoding. o Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis and sign-off quality flows. o Self-starter with strong interpersonal and communication skills . o Excellent team player. .

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Staff Design Verification Engineer Job Description In this role you will be responsible Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it functions to the standards of being launch ready for the end Product. Role And Responsibilities Partner with Architects and RTL Design team to grasp high-level system requirements and specifications. Formulate comprehensive test and coverage plans to match the Architecture and micro-architecture. Define and implement a verification methodology that supports scalability and portability across various environments spanning including post-silicon. Develop the verification environment and reusable bus functional models, stimulus, checkers, assertions, trackers, and coverage metrics. Create verification plans and develop testbenches tailored to assigned IP/Subsystem or functional domain. Execute verification plans, including tasks such as design bring-up, setting up the DV environment, running regressions for feature validation, and debugging test failures. Support post-Si bring-up and debug activities. Track and communicate progress in the DV process by using key metrics like bug tracking and coverage reports. Requirements Bachelors or Masters degree in Electrical or Computer Engineering/Science Strong Architecture domain knowledge in x86/ARM CPU, or Memory, Coherency, Virtualization or Performance areas. Must have strong expertise with SV/UVM methodology and/or C/C++ based verification with 7yrs+ hands-on experience in IP/sub-system and/or SoC level verification Hands on experience and expertise with industry standard verification tools for simulation and debug (Questa/VCS, Visualizer) Experience using random stimulus along with functional coverage and assertion based verification methodologies a must. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation. Preferred Qualifications: Experience in development of UVM based verification environments from scratch. Hands on expertise and protocol knowledge in any of: APB/AXI/CHI, JTAG/I3C/SPI, , DDR5/LPDDR5/HBM, PCIE/CXL/UCIE/Ethernet compliance testing

Apply now » .buttontext88d8dcea45dcd44d a{ border1px solid transparent; } .buttontext88d8dcea45dcd44d a:focus{ border1px dashed #5B94FF !important; outlinenone !important; } Sr Signal Integrity Engineer At TE, you will unleash your potential working with people from diverse backgrounds and industries to create a safer, sustainable and more connected world.DESIRED SKILLS Printed circuit board design (proficient in Altium a PLUS), fabrication and assembly (AutoCAD) Communication systems (high-speed servers, switches, routers, storage) Signal conditioning techniques (equalization, amplification) SixSigma methodologies or other strong data analytics background a PLUS. Experience in project leadership, especially as it applies across design, development & manufacturing teams Direct customer design and support experience Application and test knowledge of high-speed devices and equalization techniques Design experience with high-speed servers, switches, routers, storage, antenna, RF front end or similar systems Job Overview TE Connectivity’s R&D/Product Development Engineering Teams conceive original ideas for new products, introduce them into practice. They are responsible for product development, and qualification from market definition through production and release; assist in the qualification of suppliers for new products to ensure suppliers deliver quality parts, materials, and services for new or improved manufacturing processes; conduct feasibility studies, testing on new and modified designs; direct and support detailed design, testing, prototype fabrication and manufacturing ramp. The R&D/Product Development Engineering Teams provide all required product documentation including, but not limited to, Solid Model, 2D/3D production drawings, product specifications, and testing requirements. They create and modify detailed drawings and drafting or conceptual models from layouts, rough sketches or notes and contribute to design modifications to facilitate manufacturing operation or quality of product. Typical fields of expertise includematerials, mechanics and systems, electrical, optics, chemistry, software, automation systems, packaging, testing and measurement, and manufacturing of electrical, mechanical and electronic components, products, and their integration into systems. KEY RESPONSBILITIES: Drive SI design, simulation, and validation for next-gen high-speed interconnects (112G/224G PAM4, PCIe Gen6/7, Co-Packaged Optics) through the product development cycle. Conducting SI COE analysis, including o Performing signal integrity simulations and analysis for high-speed interconnect product development. This includes determining the correct simulation methodology and setup to use, as well as a good understanding of the criteria for each interface. o Modeling the connector with the consideration of manufacture impact and application impact. o Providing solutions to the SI challenges. This includes identifying the problems, making research plan, developing new technologies, and training and sharing the findings to the SI community. Develop novel interconnect solutions by optimizing mating interfaces, lead frames, and PCB transitions for resonance-free, low-loss performance. Enhance bulk cable design & termination techniques to minimize skew, impedance mismatches, and signal degradation. Advance high-frequency testing methodologies beyond 67 GHz with innovative non-PCB-based test fixtures. Utilize AI & big data analytics for predictive SI modeling, auto-routing, and performance optimization. Optimize material selection & electromagnetic design to improve noise isolation, signal integrity, and high-frequency response. Collaborate with NPD teams & industry partners to influence SI strategies, technology roadmaps, and next-gen product designs. Represent TE at industry forums (IEEE, OIF, PCI-SIG, etc.) and contribute to next-gen SI standards. Bachelor’s degree in Electrical Engineering. Should have total work experience of 3-5+years. Minimum of 5+ years of work experience in a signal integrity engineering role or related experience Minimum of 3+ years of work experience in connector development - Experience with interconnect design or experience with connector &/or cable/cable assembly design(high speed twinax cables, direct attach copper (DAC) cables) Demonstrated experience using Signal integrity analysis tools (Agilent ADS, Ansys HFSS or equivalent, 3D modeling tools) and testing equipment (including VNA, TDR and BERT). A solid understanding of statistical analysis and AI training. A solid understanding of SI knowledge, including electromagnetic theory and electrical circuit behavior Strong analytical capabilities to interpret simulation and lab data to identify issues and provide solutions to fix identified problem. Familiarity with printed circuit board design, fabrication and assembly. Familiar with material, manufacturing process, and manufacture inspection. Familiar with at least one programming language, such as Matlab, python, C++, VB, etc. Excellent verbal and written communication skills Competencies ValuesIntegrity, Accountability, Inclusion, Innovation, Teamwork .videocomponent8ae3a91ad732ccb9 a{ border1px solid transparent; } .videocomponent8ae3a91ad732ccb9 a:focus{ border1px dashed #5B94FF !important; outlinenone !important; } .buttontext13c01d781def3077 a{ border1px solid transparent; } .buttontext13c01d781def3077 a:focus{ border1px dashed #5B94FF !important; outlinenone !important; } Location: Bangalore, KA, IN, 560066 #job-location.job-location-inline {displayinline;} City: Bangalore State: KA Country/Region: IN Travel: 10% to 25% Requisition ID: 131811 Alternative Locations: Function: Engineering & Technology Job Segment Testing, Drafting, Electrical Engineering, Manufacturing Engineer, Front End, Technology, Engineering Apply now »

Apply now » .buttontext88d8dcea45dcd44d a{ border1px solid transparent; } .buttontext88d8dcea45dcd44d a:focus{ border1px dashed #5B94FF !important; outlinenone !important; } Signal Integrity Engineer At TE, you will unleash your potential working with people from diverse backgrounds and industries to create a safer, sustainable and more connected world. Job Overview TE Connectivity’s R&D/Product Development Engineering Teams conceive original ideas for new products, introduce them into practice. They are responsible for product development, and qualification from market definition through production and release; assist in the qualification of suppliers for new products to ensure suppliers deliver quality parts, materials, and services for new or improved manufacturing processes; conduct feasibility studies, testing on new and modified designs; direct and support detailed design, testing, prototype fabrication and manufacturing ramp. The R&D/Product Development Engineering Teams provide all required product documentation including, but not limited to, Solid Model, 2D/3D production drawings, product specifications, and testing requirements. They create and modify detailed drawings and drafting or conceptual models from layouts, rough sketches or notes and contribute to design modifications to facilitate manufacturing operation or quality of product. Typical fields of expertise includematerials, mechanics and systems, electrical, optics, chemistry, software, automation systems, packaging, testing and measurement, and manufacturing of electrical, mechanical and electronic components, products, and their integration into systems. Responsbilties: Drive SI design, simulation, and validation for next-gen high-speed interconnects (112G/224G PAM4, PCIe Gen6/7, Co-Packaged Optics) through the product development cycle. Conducting SI COE analysis, including o Performing signal integrity simulations and analysis for high-speed interconnect product development. This includes determining the correct simulation methodology and setup to use, as well as a good understanding of the criteria for each interface. o Modeling the connector with the consideration of manufacture impact and application impact. o Providing solutions to the SI challenges. This includes identifying the problems, making research plan, developing new technologies, and training and sharing the findings to the SI community. Develop novel interconnect solutions by optimizing mating interfaces, lead frames, and PCB transitions for resonance-free, low-loss performance. Enhance bulk cable design & termination techniques to minimize skew, impedance mismatches, and signal degradation. Advance high-frequency testing methodologies beyond 67 GHz with innovative non-PCB-based test fixtures. Utilize AI & big data analytics for predictive SI modeling, auto-routing, and performance optimization. Optimize material selection & electromagnetic design to improve noise isolation, signal integrity, and high-frequency response. Collaborate with NPD teams & industry partners to influence SI strategies, technology roadmaps, and next-gen product designs. Represent TE at industry forums (IEEE, OIF, PCI-SIG, etc.) and contribute to next-gen SI standards. Should have total work experience of 3-8+years. Minimum of 5+ years of work experience in a signal integrity engineering role or related experience Minimum of 3+ years of work experience in connector development - Experience with interconnect design or experience with connector &/or cable/cable assembly design (high speed twinax cables, direct attach copper (DAC) cables) Demonstrated experience using Signal integrity analysis tools (Agilent ADS, Ansys HFSS or equivalent, 3D modeling tools) and testing equipment (including VNA, TDR and BERT). A solid understanding of statistical analysis and AI training. A solid understanding of SI knowledge, including electromagnetic theory and electrical circuit behavior Strong analytical capabilities to interpret simulation and lab data to identify issues and provide solutions to fix identified problem. Familiarity with printed circuit board design, fabrication and assembly. Familiar with material, manufacturing process, and manufacture inspection. Familiar with at least one programming language, such as Matlab, python, C++, VB, etc. Excellent verbal and written communication skills Ability to work in a global environment – able to accommodate varying time zones, fluent in English (verbal/written), able to collaborate with individuals across geographies DESIRED SKILLS Printed circuit board design (proficient in Altium a PLUS), fabrication and assembly (AutoCAD) Communication systems (high-speed servers, switches, routers, storage) Signal conditioning techniques (equalization, amplification) SixSigma methodologies or other strong data analytics background a PLUS. Experience in project leadership, especially as it applies across design, development & manufacturing teams Direct customer design and support experience Application and test knowledge of high-speed devices and equalization techniques Design experience with high-speed servers, switches, routers, storage, antenna, RF front end or similar systems Competencies ValuesIntegrity, Accountability, Inclusion, Innovation, Teamwork .videocomponent8ae3a91ad732ccb9 a{ border1px solid transparent; } .videocomponent8ae3a91ad732ccb9 a:focus{ border1px dashed #5B94FF !important; outlinenone !important; } .buttontext13c01d781def3077 a{ border1px solid transparent; } .buttontext13c01d781def3077 a:focus{ border1px dashed #5B94FF !important; outlinenone !important; } Location: Bangalore, KA, IN, 560066 #job-location.job-location-inline {displayinline;} City: Bangalore State: KA Country/Region: IN Travel: 10% to 25% Requisition ID: 131812 Alternative Locations: Function: Engineering & Technology Job Segment Testing, Drafting, Manufacturing Engineer, Front End, CAD, Technology, Engineering Apply now »

"> Search Jobs Find Jobs For Where Search Jobs R&D Engineering, Sr Staff Engineer (VIP verification) Bengaluru, Karnataka, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 8839 Date posted 02/24/2025 Share this job Email LinkedIn X Facebook Experience : 7yrs to 12 years Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be "go-to" person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

External job description Amazon Lab126 is an inventive research and development company that designs and engineer s high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced ground-breaking devices like Fire tablets, Fire TV and Amazon Echo. Work hard. Have fun. Make history. We are looking for an Embedded Software Development Engineer- to help design, develop, integrate our next generation devices. In this role you will work with customers, system architects, program managers and hardware engineers to design, implement, troubleshoot, fix kernel drivers, Audio SW, BSP for our next generation devices. You will be responsible for the development of real-time embedded firmware and embedded Linux software that implements audio features. If you have one or more of the below skills, then this job is for you: - Expertise in ALSA / Pulse Audio - Exposure to Audio software stack on Android/QNX/proprietary OS including Audio Flinger, Audio HAL - Exposure to ARM, DSP architectures - Exposure to Dolby MS12 / DTS/ MPEG-TS - Exposure to Audio/Video Sync - Exposure to STB / DTV audio systems - Working knowledge of Oscilloscope, Logic Analyzer, and Audio Tools including Audio Precision In this role, you will: - Design audio features that work across various embedded products - Develop audio software that runs on ARM/DSP using Bare metal, Linux and other high level OSes - Optimization and porting audio and speech processing algorithms - Integration of vendor hardware and software stacks - Tune hardware for highest audio performance and lowest noise - Be passionate, responsive, flexible and able to succeed within an open collaborative peer environment - Be able and willing to multi-task and learn new technologies quickly About the team Amazon Lab126 is an inventive research and development company that designs and engineer s high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced ground-breaking devices like Fire tablets, Fire TV and Amazon Echo. - 3+ years of non-internship professional software development experience - 2+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience - Experience programming with at least one software programming language - Basic qualifications - Bachelor s degree in Computer Science or related fields - 3+ years as Application Engineering experience - 2+ years in embedded development preferably ARM systems - 5+ years programming experience in C/C++ - Linux kernel and application development, and focus on stability, efficiency, and performance. - Knowledge of Android platform and development environment. - System scripting and building environment - Experience with embedded system concepts and hardware interfaces, such as, JTAG, UART, SPI, I2C, ROM, Microcode, Custom ASIC/FPGAs x86 and ARM chipset and firmware security (TPM, UEFI, TrustZone, Secure/Measured Boot, JTAG, PCIe) - 3+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience - Bachelors degree in computer science or equivalent - Preferred qualifications - Masters or PhD - Experience supporting shipping Android and Linux based IOT devices

Youll work closely with the Purity software, hardware, NAND, and drive qualification teams. This offers a unique opportunity to learn the latest technologies, including the newest generations of NAND, NVMe/PCIe, as well as SSD controllers. Firmware development opens doors to experiences in embedded software design, hardware and system integration. Youll develop a comprehensive understanding and gain insights into the entire product development and release process. What You Will Be Doing Pure Storage is seeking a full-time Firmware Engineer to join our device firmware team. You will be working as part of a small, but fast growing, dynamic team and will be responsible for: Designing firmware simulation environment, investigating and debugging issues, and developing failure analysis tools and process Designing, implementing, and testing firmware of Pure Storage s DirectFlash SSD Modules Coding and testing in C/C++ and Python Bringing up and enabling new hardware components including latest NAND and developing low level firmware features Internal development automation including continuous integration, automated unit and regression testing, etc Working closely with hardware, system software and manufacturing teams What You Bring to the Team BS in Computer Science or equivalent Strong experience with NAND, Flash, and/or SSD Device Firmware Development Strong understanding of software/firmware test and release processes Experience using Python, C/C++ or related programming languages, hands on experience in developing the SI Familiar with embedded software or firmware development Experience with Micro-controllers, SoC, or hardware bring-up Good verbal communication & collaboration skill. Must be willing and able to work in an open office, team environment. We are primarily an in-office environment and therefore, you will be expected to work from the {{OFFICE_LOCATION}} office in compliance with Pure s policies, unless you are on PTO, or work travel, or other approved leave. WHAT YOU CAN EXPECT FROM US: Pure Innovation : We celebrate those who think critically, like a challenge and aspire to be trailblazers. Pure Growth : We give you the space and support to grow along with us and to contribute to something meaningful. We have been Named Fortunes Best Large Workplaces in the Bay Area , Fortunes Best Workplaces for Millennials and certified as a Great Place to Work ! Pure Team : We build each other up and set aside ego for the greater good.

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SMTS Verification Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer Responsibilities RESPONSIBILITIES Develop test plans, tests and verification infrastructure for complex IPs/sub-system/SOCs Create verification environment using UVM methodology Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure Work with architects, designers and post-silicon teams Qualifications Bachelors / Masters degree in Electronics/Electrical Engineering 5 to 7 year of verification experience exposure in HVL based verification with expertise in SV & OVM Exposure in High Speed IO verification (UFS/PCIE/ XUSB) Good understanding of memory technology and memory sub-system Should have knowledge on all aspects of verification components & verification closure Should have flair for documentation, defining/improving methodology and achieving productivity improvement Ability to provide technical guidance & resolving technical conflicts desired Ability to communicate technical and project issues to business and technical senior management MUST have very good verbal and written communication skills About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow s systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ .

Job Category: Design Verification Job Type: Full Time Job Location: Bangalore Requirements: Bachelor s / Master s degree in Electrical Engineering or Computer Science with 6+ years of relevant experience Verilog / System Verilog based verification experience at Subsystem and Full chip level. Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB or similar complexity bus protocols. Experience with System Verilog Assertions with industry standard tools a plus Experience with SOC bot flow, clocking and platform bring up in Emlators or Silicon Desired Experience with Low Power Verification and power management flows. Experience with RTL, GLS level simulations Knowledge and experience working on PCIE/Ethernet and other HSIO desired Experience in UVM/OVM based methodology Development. Responsibilities: Be part of a team to verify complex system on a chip designs. Interact with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using UVM/Sytem Verilog Create complex C/SV tests using reusable test libs Team player and mentor who is self-driven, motivated and guides a team of junior engineers Responsible for quality and timeliness of the team output

Understanding of White box and grey box test methods for Enterprise / Datacenter SSD Firmware is strong plus. Good hands on experience in debugging NVMe Protocol issues using Lecroy/JDSU analyzers is highly desired. Must have prepared good test plans involving access patterns, NVMe protocols, FW test hooks and VS commands for one or more following areas of FW: Front End, Back End, FTL and Security. Integrate tests into an automated test environment and collaborate with test execution teams to drive validation plans/strategy. Good Knowledge of Linux operating system debugging and Coding in Python. Effective oral and written communication with strong analytical, problem solving, and project management skills Demonstrated ability to work well with others and collaborate effectively in a team environment Expert planning and tracking skills, able to see big picture, well-organized, focused on results, capable of managing multiple projects, excellent time management with respect to priorities and self-management. Must have excellent knowledge of system storage and the relationship to the platform ingredients: CPU, Memory, PCIe, drivers, OS, firmware, etc. Education and Experience: Bachelor s or Master s degree in Computer Science or Engineering 7-11 years of experience in SSD Firmware Validation!.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Principal Duties and Responsibilities: 12+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Excellent Design verification domain expertise of min 3 years upto 6 years. Develop test strategy, TB architecture and test plan for new IP"™s/new features Develop strategies for re-useable, scalable and enhance Sub system level verification environment Excellent C/System Verilog/Verilog skills to handle C based TB environment Strong skills in debug, post silicon debug-failure re-creation and root cause analysis Scripting proficiency - PERL, Python, for developing applicable automation AMBA, AXI bus protocols Power intent verification, GLS etc. Capable of communicating effectively with all stakeholders across the globe Capable of seeding a new team for new IPs, able to hire and expand the team in expertise and efficiency Capable of mentoring the team members for their career growth, maintaining diversity in the team, collaborating with other leads and managing multiple parallel projects Take initiatives to enable various ideas for improving efficiencies. Good to have Image Processing, DSI/DP/HDMI Protocols Good knowledge of new methodologies, flows and tools to be incorporated. Formal Verification

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Chennai is looking for a VLSI engineers who is passionate in to work with cross-functional engineering teams . In this position, the engineer will be involved in all stages of the design and development cycles Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills 2-4 yrs experience Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 2 - 4 yrs of experience is preferred

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: s verification engineer candidate will be responsible to manage UFS/Ethernet/PCIe/high speed IP verification at one or more SoC (System On Chip) during project work. Responsibilities Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) . Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronics with 5+ year experience in verification domain. Prior work experience on IP level or Soc level. Prior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable. Good understanding of processor based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment. Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs). Hands on experience in UVM. C/C++ ,System Verilog verification language. Good understanding of AXI-AMBA protocol variants. Can work with scripting language (shell, Makefile, Perl ) Strong understanding of design concepts and ASIC flow. Good problem solving , analytical and debugging skill is must. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 6-9 years of experience in SoC design Educational Requirements6+ years of experience with a Bachelor"™s/ Master"™s degree in Electrical engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. The Power & Signal Integrity Group (PSIG) resides in the CHS (Central Hardware Systems) unit of Qualcomm Technologies, Inc., a leader in wireless communication technology. Engineers in the Power & Signal Integrity Group work with the various business units across Qualcomm to help bring leading edge mobile, AR\VR, IoT, Automotive and various others products to market. The candidate will work in a team-oriented environment with cross functional leads to provide electrical design expertise in the areas of signal integrity and power integrity for the design of wireless products and development systems. The engineer will be located in Bangalore, India and will be closely working with the Product architects, Platform HW teams, IO\PHY, IC Packaging, and other teams. The candidate is expected to perform SI / PI analyses and provide guidance on signal and power integrity challenges. Working effectively across organizational boundaries is essential as is the effective documentation and presentation of results. The candidate is expected to work closely with an experienced SI engineer while applying established PSIG methodologies. The engineer will have the opportunity to influence the evolution of analysis methodologies. Responsibilities Perform various IO analyses using established methodologies, potentially from model extraction through simulation and reporting of conclusions. IO types include DDR memory interfaces and variety of serial interfaces. Analyze and provide design guidance for DIE floor plans, IC packages, PCB power distribution networks using established methodologies. Document, distribute, and present results at appropriate meetings. 2+ years of work experience in the following areas: Electromagnetic theory and transmission lines Basic signal and power integrity concepts Commercial 3D electromagnetic field solver Commercial SI or RF simulation and analysis tools SPICE transient simulation including use of IBIS models The following experience is a plus: DDR and LPDDR design and analysis High speed serial IO design and analysis, PCIE, USB, UFS, CSI/DSI/MIPI Power Integrity analysis SI/PI tools :Ansys HFSS/SIwave, Cadence/Sigrity, Keysight ADS, HSPICE Spreadsheets and similar productivity tools Mentor or Cadence board design tools Education Requirements: Minimum Bachelor degree in Electrical Engineering or related discipline, Master degree preferred

Design verification SOC Verification UVM, OVM Verilog, System Verilog Test Bench, Test cases

As a FPGA Verification Engineer at Nokia, you will work for a high complexity DWDM equipment for LH/ULH applications. You will work in close collaboration with multi location cross-functional R & D teams. Our work includes everything from product concept to finished product - a process that spans over the entire development cycle. The team takes full responsibility for delivery on time with the right quality. This role typically requires 3-6 years of experience developing SystemVerilog UVM-based test environments and implementing comprehensive test plans - at block, sub-chip and chip levels Strong proficiency in Hardware Verification Languages (HVL), with practical coding experience for verification tasks Practical experience using industry-standard simulators such as VCS, NC-Sim, or ModelSim (MTI), along with strong skills in waveform-based debugging. Solid understanding and practical application of UVM or similar modern verification methodologies. Experience with scripting languages such as Perl is highly valued and will help you stand out. It would be nice if you also had: Working knowledge of RTL design and familiarity with technologies like Ethernet, PCIe, and preferably telecom protocols. Strong analytical, troubleshooting, and problem-solving skills, with a structured and thorough approach to work. Good written and oral communication skills are required. Excellent written and verbal communication skills. Flexible, innovative, and self-driven team player with a strong willingness to take initiative. Design and develop comprehensive FPGA verification plans. Create and implement verification environments and testbenches. Develop and execute test scenarios for running simulations. Perform coverage analysis to ensure thorough verification. Provide lab support during FPGA and board bring-up phases. Collaborate closely with design and system teams to drive verification solutions. Independently manage verification tasks and projects. What We Offer: Opportunity to work in short product development cycles, allowing you to quickly see the real impact of your contributions on products and business success. International career development opportunities with internal mobility programs that encourage professional growth and advancement within the company. Access to a variety of social, wellness, and hobby clubs to support a balanced lifestyle and foster a sense of community. A friendly, inclusive, and supportive atmosphere where collaboration and mutual respect are core values. The chance to work alongside highly skilled, motivated, and innovative colleagues who are passionate about technology and excellence.

"> Search Jobs Find Jobs For Where Search Jobs R&D Engineering, Staff Engineer - IP Verification Noida, Uttar Pradesh, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 7271 Date posted 02/24/2025 Share this job Email LinkedIn X Facebook Experience : 5yrs to 10 years Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective Locally should be to be "go-to" person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

"> Search Jobs Find Jobs For Where Search Jobs R&D Engineering, Staff Engineer (VIP verification) Noida, Uttar Pradesh, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 8828 Date posted 02/24/2025 Share this job Email LinkedIn X Facebook Experience : 5yrs to 12 years Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be "go-to" person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

"> Search Jobs Find Jobs For Where Search Jobs Solutions Engineering, Sr Staff Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10799 Remote Eligible No Date Posted 21/04/2025 Experience level: 8 to 12 Yrs Are you ready for a new and exciting challengeIf you are a self-motivated SoC Verification Engineer with expertise in SoC architecture and looking to make a difference in an innovative and inclusive team, you ve come to the right place! Job Overview: We are seeking a highly skilled and experienced SoC validation expert to join our growing team. The ideal candidate will be working on various industry-based like mobile, server etc. System on Chip (SoC) designs containing custom hardware subsystem and transactors. Responsibiliti es: This challenging position will offer you the opportunity to work with Synopsys advanced technology in a collaborative environment to: Develop validation environment on various industry-based SoC design on Emulation/FPGA and/or Virtual environments. Collaborate with Design SoC, Solutions and Synopsys IP team. Collaborate across complementary teams to develop and trace system requirements, functionality and Performance environment. Align with the development work taking place across multiple teams. This includes steering the development of functional and performance test plans, environment and supporting the E mulation/FPGA, Solutions and IP team. Stay up to date with the latest advancements in semiconductor design and Emulation technology to drive innovation and continuous improvement. Mentor to junior engineers and team members Work with engineering teams to improve various workloads Required Skills & Experience: Bachelor s or Master s in Electronic Engineering, Electrical Engineering, Computer Engineering, VLSI, or related field. Minimum 8 years in SoC Validation. Have emulation experience in Zebu/Haps or equivalent platforms. Have HW RTL verification and debugging expertise. Design & Develop test environment having various debug hooks and automation. High speed protocols (such as USB, PCIe, UFS or LPDDR technology) knowledge/expe rience is a plus. Able to work independently with minimal supervision, Lead the team technically, Capable of mentoring and developing a strong team. "Nice To Have" Skills & Experience: Excellent communication (written, verbal, presentation) skills. Proven track record of generating consistent, complete, and concise written s pecifications. Motivated to continuously develop skills, development processes, and improve results At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

An experienced and passionate ASIC Digital Verification Engineer with a deep understanding of RTL-based IP cores and complex protocols. You have over 12 years of experience in functional verification and are adept at making architectural decisions for test bench designs. You are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), and you have a proven track record of implementing coverage-driven methodologies. You bring a wealth of knowledge in protocols such as DDR, PCIe, AMBA, and more. Your technical expertise is matched by your strong communication skills, ability to work independently, and your innovative problem-solving capabilities. Your experience may also include familiarity with functional safety standards such as ISO26262 and FMEDA. What You ll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms. Mentoring and guiding junior engineers in the verification domain. What You ll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure. Proficiency in SystemVerilog and UVM, object-oriented coding, and verification. Experience with scripting languages like C/C++, TCL, Perl, Python. Experience with functional safety standards such as ISO26262 and FMEDA (preferred). Who You Are: Independent and precise in your work. Innovative and proactive in problem-solving. Excellent communicator and team player. Detail-oriented with a strong analytical mindset. Eager to learn and grow within a technical role

* Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification of all its functions, covering both the Controller and PHY. * Reporting metrics and driving improvements in Emulation IP. * Using your expertise to drive requirements for the Emulation IP and ensure its correct usage and deployment in verification strategies for both Controller and PHY. * Staying ahead of evolving standards, understanding future changes, specification errata, and driving this understanding into both the Emulation IP and Design IP teams. * Reviewing test plans in both Emulation IP and Design IP to ensure they deliver the required function, feature, and quality to be best in class. The Impact You Will Have: * Enhancing cross-functional collaboration to improve product quality and end customer satisfaction. * Changing the mindset in the way we use Emulation IP in validating digital designs and architectures. * Driving innovation in defining requirements for IP product development, in the context of Emulation. * Evolving and integrating best-in-class methodologies within the organization. * Standardizing and optimizing workflows to increase efficiency and compliance. What You ll Need: * 10+ years of relevant experience. * Results-driven mindset. * Exposure on advanced protocols like PCIe and DDR interfaces. * Experience with Zebu in the context of technology and IP verification. * Proven track record in IP product development, specifically emulation. * Experience in cross-functional collaborations. * Excellent communication skills and a beacon for change. * Adaptability and comfort in a matrixed, international environment.