GPU Design Verification Engineer, Silicon

Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience 4 years of experience with standard GPU workloads like Manhattan/3DMark Experience with GPU architecture and AMBA bus protocols like AHB/AXI/ACE Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field Experience in low-power design verification Experience with performance verification of ASICs and Application-Specific Integrated Circuit (ASIC) components About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration As a GPU Design Verification Engineer, you will be focusing on the pre-silicon verification of complex, high-performance GPU subsystems You will be responsible for defining verification strategy, developing robust constraint-random environments, and driving coverage closure for our most critical GPU design blocks using skills like SystemVerilog/Universal Verification Methodology (UVM) The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world Responsibilities Be part of a team to verify digital design blocks (eg CPU, Graphics Processing Unit (GPU), Image processor) by understanding the design specification and interacting with design engineers to identify important verification scenarios Create and enhance constrained random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools Identify and write all types of coverage measures for stimulus and corner cases Debug tests with design engineers to deliver functionally correct design blocks Close coverage measures to identify verification holes and to show progress towards tape-out Google is proud to be an equal opportunity workplace and is an affirmative action employer We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form