1121 Dft Jobs - Page 41

Job Description onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. onsemi’s Core-Analog IP Center of Excellence is hiring an experienced Analog IC design engineer to help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex CMOS integrated circuits and have familiarity with analog blocks such as bandgaps, amplifiers, filters, precision comparators, LDOs, oscillators, PLLs etc. Experience with signal chain optimization is highly desired. Key Duties & Responsibilites Must have a working knowledge of Cadence Circuit design tools. Analytical approach to problem solving is required. CMOS designs provide challenging learning opportunities where performance, power and reliability are all pushed to the limit while maintaining product execution schedule. Drive development and verification of state-of-the-art analog blocks and mixed signal CMOS designs which can be reused across different market segments. Participate in analog circuit requirements discussions, technical issues and other design aspects to arrive at agreed upon product specifications. Build/develop circuits based on an IP specification, drive the layout design and final IP characterization. Execute state-of-the-art analog designs while following the best design practices with on time quality design releases. Propose innovative and creative solutions where necessary to meet customer & product needs. Work diligently with the given requirements to accomplish project goals and meet schedule requirements. Debug of complex integrated circuit problems in the laboratory. Collaborate in debug efforts as needed. Perform bench characterization and support application engineering bench evaluation efforts. Analyze design aspects related to DFT and collaborate with other team members to develop DFT strategy for block designs. Document designs including architecture and circuit descriptions, testing procedures, and safety mechanisms. Interface with test, product, and applications engineering to drive the design to a successful production release. Qualifications Requirements Analog design experience in verification, documentation, and post-silicon validation. Includes broad understanding of integrated circuit design such as amplifiers, filters, BGAP circuits, oscillators etc. In-depth knowledge of semiconductor devices like MOS transistors, BJTs etc. Knowledge with behavioral top-level modeling and mixed signal verification methodology. Knowledge of UNIX/Linux working environment Knowledge of multiple semiconductor design tools like Matlab, Spectre, Spice, Cadence design environment. AMS simulation experience is a plus. Excellent written and oral communication. Proven ability to work independently and in teams. Hands-on experience in a lab environment working with sensitive measurement equipment and data acquisition. Very good debugging ability in circuit operation, and device function Master’s degree in Electrical Engineering with 5+ years of relevant experience or Ph.D. in Electrical Engineering with 3+ years of relevant experience in analog circuit design. About Us onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. More details about our company benefits can be found here: https://www.onsemi.com/careers/career-benefits About The Team We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work. onsemi is an Equal Opportunity and Affirmative Action employer. The Company maintains policies and practices that are designed to prevent discrimination or harassment against any qualified applicant or employee to the extent prohibited by federal, state and local laws and regulations. By way of example, discrimination on the basis of race (actual or perceived), ethnicity, color, religion, ancestry, national origin, citizenship, sex, age, marital status, sexual orientation, physical or mental disability, medical condition, genetic information, military or veteran status, gender identity, gender expression, or any other characteristic protected by applicable law is prohibited. If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Talent.acquisition@onsemi.com for assistance. Show more Show less

L&T Technology is hiring for Senior DFT Engineers / Lead DFT Engineer with 8-15 Years of experience. Job Location : Bangalore Skills Expertise should be : ATPG, SOC, ASIC DFT. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. Must be able to obtain and maintain a Department of Defense classified clearance Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT) Should possess intimate knowledge of DFT insertion flows Basic scan chain insertion using synthesis or other software tools Experience in compression scan insertion, LBIST and other scan technologies Intimate knowledge of memory build-in self-test (MBIST) Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals Debug and Analysis of failures to improve fault coverage Verification of ATPG testbenches and debugging root cause of simulation mis-compares Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687 Knowledge of timing analysis and equivalency checks would be added bonus Ability to work in collaborative team environment Prior experience with Cadence tools and flows is highly desirable Should be able to finish DFT tasks independently Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers Self-driven and committed individual who can work in a fast-paced project environment We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position: Sr Principal Software Engineer Grade: T5 Location: Noida Job Responsibilities The role’s day to day responsibilities cover: R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications BE/BTech/ME/MTech- Computer Science or others Experience: 11-15 Yrs Required Skills Develop reliable, scalable, and high-performance Modus DFT software that is easy to use. Develop software tools in C/C++ to support DFT and ATPG. Research and develop software solutions to allow greater efficiency in architecture, hardware, and software teams. Development environment is C++ on Unix in multi-threaded environment with expertise in C++, data-structure and algorithms. Strong knowledge of Tcl is preferred Experience in language compiler Prior experience with large software development projects is highly recommended. We’re doing work that matters. Help us solve what others can’t. Show more Show less

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Alphawave Semi is expanding its team in Chiplet Architecture and Design! We are looking for experienced RTL Design Engineers to contribute to our next generation Chiplet designs. This is an incredible opportunity to be part of the AI revolution and contribute to the complete ASIC development cycle, from concept to product. As an RTL Design Engineer, you will work in SoC design and SOC-Subsystem design. You will be responsible for microarchitecture/RTL coding of the SOC/subsystems and create microarchitecture documents. You will work with verification teams on achieving the code & functional coverage. You will work with Physical design team to meet area, power and performance goals. You will support physical design teams, verification teams, software teams and FPGA teams to ensure high quality SoC and ensure successful tapeout. What You'll Do : Micro architect and RTL Design of SoC SubSystem/IP blocks Will develop UPF and run CLP checks Will be responsible for RTL quality checks - Lint/CDC/LEC Create appropriate documentation for hardware blocks. Responsible for analyse / debug / fixing issues reported by verification team Will develop the synthesis constraints for the blocks / subsystem Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation What You'll Need: Education: Bachelor's or master's degree in electrical or Electronics and Communication or Computer Science Engineering. Experience: 14+ years of proven experience in SoC architecture, development, and full-chip design for multi-million gate SoCs. Expertise: Strong understanding of the design convergence cycle, including architecture, micro-architecture, verification, synthesis and timing closure. Expertise in managing IP dependencies, as well as planning and tracking front-end design tasks. Ability to drive project milestones across design, verification, and physical implementation phases. Experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains is highly desirable. Skills: Excellent communication and interpersonal skills. Ability to collaborate in a fast-paced, product-oriented, and distributed team environment. Minimum Qualifications: SoC Design Experience: Minimum 14+ years of hands-on experience in SoC design. Architecture Development: Ability to develop architecture and micro-architecture based on specifications. Bus Protocols & Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc. Memory Controllers & Microprocessors: Experience with memory controller designs and microprocessors is an advantage. Chip IO Design: Knowledge of chip IO design and packaging is beneficial. Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics. Synthesis & Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC. Timing Closure: Comprehensive understanding of timing closure is mandatory. Post-Silicon Debug: Experience in post-silicon bring-up and debugging. Decision Making: Ability to make effective decisions under incomplete information. Communication & Leadership: Strong leadership and communication skills to ensure effective program execution. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Great compensation package Restricted Stock Units (RSUs) Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities Implementation of DFT features into RTL using verilog. Understanding of DFT Architectures and micro-architectures. ATPG and test coverage analysis using industry standard tools. JTAG, Scan Compression, and ASST implementation. Gate level simulation using Synopsys VCS and Verdi. Support silicon bring-up and debug. MBIST planning, implementation, and verification. Support Test Engineering on planning, patterns, and debug. Develop efficient DFx flows and methodology compatible with front end and physical design flows Experience & Qualifications BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques. DFx experience implementing in finFET technologies. Experience with industry standard ATPG and DFx insertion CAD tools. Familiarity with SystemVerilog and UVM. Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors. Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling. Good understanding of high-performance, low-power design fundamentals. Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. Exposure to post-silicon testing and tester pattern debug are major assets. Experience with Fault Campaigns a plus. Strong problem solving and debug skills across various levels of design hierarchies. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. Show more Show less

Description Amazon Devices is an inventive research and development company that designs and develops high-profile devices like the Kindle family of products, Fire Tablets, Alexa, Fire TV, Health Wellness, Amazon Echo & Astro products. This is an exciting opportunity to join Amazon in developing its next generation SOC’s for the machine learning enabled consumer products. We are looking for exceptional engineers and engineering leaders to join our SOC development team and help develop the next generation of chips based on a revolutionary architecture. The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Integration Design Engineer to continue to innovate on behalf of our customers. Work hard. Have Fun. Make history. Key job responsibilities In this role, you work in a team developing SoCs to be deployed in a range of Amazon devices. You will integrate industry standard and custom hardware IP and subsystems into SoCs to accelerate applications in machine learning, computer vision and robotics. You will work closely with System Architects, SoC architects, IP developers and physical design teams to develop SoCs that meets the power, performance and area goals for Amazon devices. You will help define the processes, methods and tools for design and implementation of large complex SoCs. Develop chip level and subsystem level netlists integrating IPs and new design. Work with Chip Architects to understand architecture and high-level product requirements. Convert Chip Spec into RTL using internal IPs and external IPs. Review Architecture and Design of custom IPs for integration into SOC’s. Design & Develop RTL for Interfaces, Power Management, Clocking, Reset, Test & Debug. Develop and implement methodologies for I/O, DFT, Debug, Clocking and Power Management. Provide technical leadership through lead by example, mentorship and strong team work. Basic Qualifications BS degree or higher in EE or CE or CS 5+ years or more of practical semiconductor design experience including full-chip and subsystem RTL integration. Experience in micro-architecture definition from architecture guideline and model analysis. Experience in RTL coding (Verilog/System Verilog) and debug, as well as performance/power/area analysis and trade-offs Experience in closing full-chip and subsystem timing working with synthesis and static timing analysis teams. Experience with DFT tools for scan and BIST insertion Excellent verbal and written communication skills, collaboration and teamwork skills as well as ability to contribute to diverse and inclusive teams. Preferred Qualifications MS or PhD degree in Computer Engineering/Electrical Engineering or related field. Design experience in Datapath, flow control, Arbitration, FIFO, DMA , IOMMU, SOC bus architectures, Arteris NOC interconnect, ARM’s AXI/AHB bus architecture & Protocols, Serial interfaces such as PCIe, QSPI, I2C,UART, EMMC, USB. LPDDR controller & Phy IP integration, embedded memory (SRAM, OTP etc;.) Other IP integration such as ADC, PLL, DLL, PVT sensors, GPIO & Debug (Coresight). In-depth knowledge of in one or more areas such as CPU, DSP, or programmable accelerators. SOC bring-up and post silicon validation experience Experience with early RTL power analysis. Experience with gate level testing and multi clock design practices. Successful tape outs of complex, high-volume SoCs in advanced design nodes Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. Company - ADCI - BLR 14 SEZ Job ID: A2914332 Show more Show less

Job Description We are currently developing a Transport Modelling team in Mott MacDonald’s Global Delivery Services (GDS) in Bangaluru, India and are looking to recruit Transport Modellers for the team. In the role you will be involved with a range of transport modelling projects working with our existing teams based across the UK. You will be working on projects for high profile clients such as East West Rail Ltd, Heathrow Airport, HS2 Ltd and National Highways and will have responsibility for delivering modelling work following our best practice guidelines. Your responsibilities will include but are not limited to the following: Working on highway and strategic multi-modal modelling projects; Involvement in projects including survey programmes, model development, calibration, validation, demand forecasting and economic appraisal; Checking outputs for compliance with quality requirements and industry best practice; Provide key inputs to the development of business cases and scheme assessments; Liaise with clients and other project stakeholders; Contribute to business development activities including proposal preparation. Person Specification As a Transport Modeller, you will be committed to providing high quality, affordable and innovative solutions. Ideally you will already have experience working in a Global Delivery teams facing UK clients. To Carry Out The Responsibilities We Will Require Numerate degree (or equivalent) ideally in a transport related discipline.Master degree is advantageousbut not essential; Good experience using SATURN modelling software; An understanding of the requirements of the UK DfT’s TAG guidance and evidence of implementation on projects; Experience of using UK DfT software such as DIADEM, TUBA, WITA; Experience of survey design and data analysis skills; An understanding of variable demand modelling and forecasting. The Following Would Also Be Desirable But Not Essential Expertise in Geographic Information System (GIS); Experience in the use of other software such as VISUM, CUBE or EMME; Knowledge of microsimulation software such as VISSIM, PARAMICS, AIMSUN; Coding/scripting/database skills. We Can Offer (subject To Company’s Policy) Agile and safe working environment Competitive annual leave and sick leaves Group incentive scheme Group term life insurance, Workmen’s compensation and Group medical insurance coverage Short and Long-term Global employment opportunities Global collaboration and knowledge sharing Digital Innovation and Transformation Equality, diversity and inclusion We put equality, diversity and inclusion at the heart of our business, seeking to promote fair employment procedures and practices to ensure equal opportunities for all. We encourage individual expression in our workplace and are committed to creating an inclusive environment where everyone feels they have the opportunity to contribute. Agile working At Mott MacDonald, we believe it makes business sense for you and your manager to choose how you can work most effectively to meet your client, team and personal commitments. We embrace agility, flexibility and trust. Location(s): Bengaluru, KA, IN Contract Type: Permanent Work Pattern: Full Time Market: Transport Discipline: Planning and modelling Job Ref: 7533 Recruiter Contact: Naveen Gill Show more Show less

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We don’t need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 2-5 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday Show more Show less

Job Description Change the world. Love your job. Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. Additional job functions include analyzing equipment to establish operating data and conducting experimental tests and evaluating results to confirm the device meets all requirements in the specifications. You may also run software simulations, selecting components and equipment based on analysis of specifications and reliability. As a Design Verification Engineer you may also review vendor capability to support product development. Requires a BS degree or equivalent experience in the design of equipment, components or circuitry. About ASM Auto ASM (Application specific Microcontroller) business powers automotive and industrial MCU across multiple applications. ASM is now working on next generation Automotive MCU platform for all kind of vehicle applications e.g. Traction motor control, Charging, Lighting and Heating control, IC Engine management etc. This platform will churn out multiple differentiated products for Zonal networking in Software defined Vehicles (SDV) and superior real time control for EV Cars. Great opportunity to be part of this grounds up platform development across process nodes, IPs and SoCs. https://www.ti.com/applications/automotive/overview.html Responsibilities Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes: Active involvement with architecture team during the spec definition phase Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics SubSystem/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes. DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs Active collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities Final SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines Qualifications Qualifications: 2-5 years of DV experience in SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations Skills Experience in one or many of the following: C based SOC DV, scripting (Python/Perl/Shell) knowledge, DV flow ownership for functional/Formal verification, UVM/System Verilog deep understanding, AMS/GLS/PAGLS/CPF/UPF based verification, Post silicon verification etc. Strong in digital design fundamentals, computer organization & architectures and bus protocols Excellent debugging skills with Verilog/VHDL designs Thorough knowledge in one or many of the standard protocols. Ex: AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, PSI5, Flexray etc Work experience on C based environment with ARM/DSP multi-processor-based systems including the power aware simulations is a big plus Good problem-solving skills Experience with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flows Exposure to CDC DV, Post silicon verification and functional safety is an added advantage Effective communication skills to interact seamlessly with all stakeholders Must be highly focused and remain committed to obtaining closure on project goals About Us Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. About The Team TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment. Show more Show less

Roles & Responsibilities:- Lead the architecture, design, and validation of power converters and electrical hardware platforms. Perform feasibility studies, design calculations, thermal analysis, and component selection. Conduct detailed PCB layout reviews Ensure IPC compliance, signal and power integrity, and manufacturing best practices, Identify and correct layout faults and cosmetic issues. Collaborate with outsourcing partners for hardware design and manufacturing execution. Drive hardware integration, ensuring system-level electrical performance. Focus on innovation initiatives including new converter topologies, design optimizations, and reliability enhancements. Lead technical design reviews, mentor junior engineers, and define internal hardware standards. Support EMC testing, HALT/HASS reliability testing, and regulatory compliance. Key Result Areas: Delivery of robust, high-efficiency power and control hardware architectures. Advancement of innovation initiatives within hardware development. Quality assurance and management of outsourced design and manufacturing partners. Development and enforcement of internal hardware review frameworks and documentation standards. Technical leadership and capability building across the hardware engineering team. Internal: Lead the delivery of high-efficiency power and control hardware architectures across projects. Drive innovation initiatives such as new converter topologies, design optimization, and advanced reliability methods. Establish and enforce hardware review frameworks, DFM/DFT standards, and documentation practices. Mentor and develop internal engineering capabilities through technical leadership and structured reviews. External: Manage collaboration with outsourcing partners for hardware design, manufacturing, and validation. Ensure outsourced work meets internal quality standards, design specifications, and timeline requirements. Lead technical reviews of externally developed designs for IPC compliance, manufacturability, and signal integrity. Coordinate with external suppliers and manufacturers to secure customized components and ensure smooth prototype and production deliveries. Educational Qualification: •Bachelor's or Master’s degree in Electrical Engineering, preferably with specialization in Power Electronics. Required Skills: Expertise in power converter design across major topologies. Strong proficiency in digital and analog control circuit design. Extensive experience in PCB layout reviews emphasizing signal integrity, power distribution, and IPC compliance. Practical knowledge of Design for Manufacturing (DFM) and Design for Testability (DFT). Hands-on with PCB CAD tools (Altium Designer, Cadence Allegro) and Signal Integrity simulation software. Vendor management experience for external hardware development. Strong leadership, technical documentation, communication, and mentoring abilities. Show more Show less

Roles & Responsibilities:- Lead the architecture, design, and validation of power converters and electrical hardware platforms. Perform feasibility studies, design calculations, thermal analysis, and component selection. Conduct detailed PCB layout reviews Ensure IPC compliance, signal and power integrity, and manufacturing best practices, Identify and correct layout faults and cosmetic issues. Collaborate with outsourcing partners for hardware design and manufacturing execution. Drive hardware integration, ensuring system-level electrical performance. Focus on innovation initiatives including new converter topologies, design optimizations, and reliability enhancements. Lead technical design reviews, mentor junior engineers, and define internal hardware standards. Support EMC testing, HALT/HASS reliability testing, and regulatory compliance. Key Result Areas: Delivery of robust, high-efficiency power and control hardware architectures. Advancement of innovation initiatives within hardware development. Quality assurance and management of outsourced design and manufacturing partners. Development and enforcement of internal hardware review frameworks and documentation standards. Technical leadership and capability building across the hardware engineering team. Internal: Lead the delivery of high-efficiency power and control hardware architectures across projects. Drive innovation initiatives such as new converter topologies, design optimization, and advanced reliability methods. Establish and enforce hardware review frameworks, DFM/DFT standards, and documentation practices. Mentor and develop internal engineering capabilities through technical leadership and structured reviews. External: Manage collaboration with outsourcing partners for hardware design, manufacturing, and validation. Ensure outsourced work meets internal quality standards, design specifications, and timeline requirements. Lead technical reviews of externally developed designs for IPC compliance, manufacturability, and signal integrity. Coordinate with external suppliers and manufacturers to secure customized components and ensure smooth prototype and production deliveries. Educational Qualification: •Bachelor's or Master’s degree in Electrical Engineering, preferably with specialization in Power Electronics. Required Skills: Expertise in power converter design across major topologies. Strong proficiency in digital and analog control circuit design. Extensive experience in PCB layout reviews emphasizing signal integrity, power distribution, and IPC compliance. Practical knowledge of Design for Manufacturing (DFM) and Design for Testability (DFT). Hands-on with PCB CAD tools (Altium Designer, Cadence Allegro) and Signal Integrity simulation software. Vendor management experience for external hardware development. Strong leadership, technical documentation, communication, and mentoring abilities. Show more Show less

Senior SoC Director / SoC Director Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in AI Accelerators DNN Accelerators co-processors Interconnect Fabric Cache Coherency D2D C2C SoC Director Bangalore We are a AI semiconductor startup company headquartered in Ann Arbor, Michigan, with branches in , Taiwan and Bangalore, India. We develop highly scalable and innovative AI accelerator chips that offer high performance, low energy, and customer ease of implementation for embedded Edge AI vision-based applications and real-time data processing. Company has working HW & SW for customer sampling, with production designs in the pipeline, and a system architecture designed a future of neuromorphic computing. We are backed by excellent VC funding and is currently in a stage of rapid growth. While our tech is one of a kind we would not be able to make these advancements without our team. Our collaborative culture is one of the keys to our success. Who You Are You are an open and honest communicator who values your team You are innovative, enjoy bringing new ideas to the table and are receptive to ideas and feedback from others You’re passionate about advancing the state of the world through new technology You enjoy the ambiguity and pace of a startup environment The role This leadership role will be responsible for the global VLSI efforts at and India Site Management. It is a highly visible role reporting to Senior Director with ownership of all pre/post Si activities, leading interface with external EDA, IP, Design Service partners, managing the India site operations and a global VLSI team. What you will be doing: Ownership of pre-Si Design of the next-gen AI accelerator at driving deliverables with Design and IP Service providers, CAD tools, IPs, DFT/PD/Packaging and Test. Work closely with internal Architecture, SW, Emulation, and system board designers on product definition, microarchitecture, and design implementation. Build and manage the VLSI team of front-end design and verification engineers across India and Taiwan. Establish best practices for development, testing, reviews, and documentation. Participate in strategic discussions for product features and roadmap. What we expect to see: BS/MS in Electrical/Electronic Engineering with 18+ years of experience in VLSI, SOC design, several Si tape-out/production. Hands-on experience in front-end design, VLSI flows, and working experience for all aspects of Si tape-out, post-Si validation. Self-driven, organized with strong leadership and communication skills. Experience in building and managing teams with the ability to motivate and lead in a startup environment. Proven track record in several successful productizations. What we would be happy to see: Knowledge of AI, specifically Deep Neural Networks Application-specific accelerators or co-processors Startup experience Site Leadership experience Reports to: Site Lead Work location: Bangalore, India Hours: Full time Employment Opportunity and Benefits of Employment: We are committed to creating and fostering a diverse and inclusive workplace environment for all of our employees. We are an equal opportunity employer. Contact: Uday Mulya Technologies Email: muday_bhaskar@yahoo.com Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Alphawave Semi is expanding its team in Chiplet Architecture and Design! We are looking for experienced RTL Design Engineers to contribute to our next generation Chiplet designs. This is an incredible opportunity to be part of the AI revolution and engage in the complete ASIC development cycle, from concept to product. We are seeking a seasoned SoC leads to work with a team to solve complex problems while optimizing performance, area, and power on leading-edge SoC systems. This team helps build new and innovative connectivity products tailored to world changing solutions for AI accelerators, Compute, IO, and Memory Chiplets. What You'll Do: You will manage the design / RTL team to achieve the project goals You will work with customer, provide technical support and provide collaterals agreed upon. You will work with team to achieve flow, methodology improvements to achieve high reuse. You will work with IP vendors to generate / get right configurations of the IP. You will manage teamwork allocation, schedule, risk mitigation and deliverables from design team. Interact closely with the architecture team and develop implementation strategies to meet quality, schedule, and power performance area for the SOC. Interact with the subsystem team and plan SOC milestones, plan quality checks as part of SOC milestones and guide subsystem teams with SOC level requirements (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.). Work with the cross-functional team of verification, DFT, Physical Design, emulation, and software teams to make design decisions and represent Design status throughout the development process. What you'll have: Education: Bachelor's or master's degree in electrical or Electronics and Communication or Computer Science Engineering. Experience: 15+ years of proven experience in SoC architecture, development, and full-chip design for multi-million gate SoCs. Expertise: Strong understanding of the design convergence cycle, including architecture, micro-architecture, verification, synthesis and timing closure. Expertise in managing IP dependencies, as well as planning and tracking front-end design tasks. Ability to drive project milestones across design, verification, and physical implementation phases. Experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains is highly desirable. Skills: Excellent communication and interpersonal skills. Ability to collaborate in a fast-paced, product-oriented, and distributed team environment. Minimum Qualifications: SoC Design Experience: Minimum 15+years of hands-on experience in SoC design. Architecture Development: Ability to develop architecture and micro-architecture based on specifications. Bus Protocols & Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc. Memory Controllers & Microprocessors: Experience with memory controller designs and microprocessors is an advantage. Chip IO Design: Knowledge of chip IO design and packaging is beneficial. Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics. Synthesis & Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC. Timing Closure: Comprehensive understanding of timing closure is mandatory. Post-Silicon Debug: Experience in post-silicon bring-up and debugging. Decision Making: Ability to make effective decisions under incomplete information. Communication & Leadership: Strong leadership and communication skills to ensure effective program execution. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Great compensation package Restricted Stock Units (RSUs) Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Alphawave Semi is expanding its team in Chiplet Architecture and Design! We are looking for talented RTL Design Engineers to contribute to our next generation Chiplet designs. This is an incredible opportunity to be part of the AI revolution and engage in the complete ASIC development cycle, from concept to product. As an RTL Design Engineer, you will work in SoC design and SOC-Subsystem design. You will be responsible for microarchitecture/RTL coding of the SOC/subsystems and create microarchitecture documents. You will work with verification teams on achieving the code & functional coverage. You will work with Physical design team to meet area, power and performance goals. You will support physical design teams, verification teams, software teams and FPGA teams to ensure high quality SoC and ensure successful tapeout. What You'll Do: Micro architect and RTL Design of SoC SubSystem/IP blocks Will develop UPF and run CLP checks Will be responsible for RTL quality checks - Lint/CDC/LEC Create appropriate documentation for hardware blocks. Responsible for analyse / debug / fixing issues reported by verification team Will develop the synthesis constraints for the blocks / subsystem Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation What You'll Need: Education: Bachelor's or master's degree in electrical or Electronics and Communication or Computer Science Engineering. Experience: 5+ years of proven experience in SoC architecture, development, and full-chip design for multi-million gate SoCs. Expertise: Strong understanding of the design convergence cycle, including architecture, micro-architecture, verification, synthesis and timing closure. Expertise in managing IP dependencies, as well as planning and tracking front-end design tasks. Ability to drive project milestones across design, verification, and physical implementation phases. Experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains is highly desirable. Skills: Excellent communication and interpersonal skills. Ability to collaborate in a fast-paced, product-oriented, and distributed team environment. Minimum Qualifications: SoC Design Experience: Minimum 5+ years of hands-on experience in SoC design. Architecture Development: Ability to develop architecture and micro-architecture based on specifications. Bus Protocols & Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc. Memory Controllers & Microprocessors: Experience with memory controller designs and microprocessors is an advantage. Chip IO Design: Knowledge of chip IO design and packaging is beneficial. Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics. Synthesis & Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC. Timing Closure: Comprehensive understanding of timing closure is mandatory. Post-Silicon Debug: Experience in post-silicon bring-up and debugging. Decision Making: Ability to make effective decisions under incomplete information. Communication & Leadership: Strong leadership and communication skills to ensure effective program execution. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Great compensation package Restricted Stock Units (RSUs) Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Alphawave Semi is expanding its team in Chiplet Architecture and Design! We are looking for experienced RTL Design Engineers to contribute to our next generation Chiplet designs. This is an incredible opportunity to be part of the AI revolution and contribute to the complete ASIC development cycle, from concept to product. As an RTL Design Engineer, you will work in SoC design and SOC-Subsystem design. You will be responsible for microarchitecture/RTL coding of the SOC/subsystems and create microarchitecture documents. You will work with verification teams on achieving the code & functional coverage. You will work with Physical design team to meet area, power and performance goals. You will support physical design teams, verification teams, software teams and FPGA teams to ensure high quality SoC and ensure successful tapeout. What You'll Do: Micro architect and RTL Design of SoC SubSystem/IP blocks Will develop UPF and run CLP checks Will be responsible for RTL quality checks - Lint/CDC/LEC Create appropriate documentation for hardware blocks. Responsible for analyse / debug / fixing issues reported by verification team Will develop the synthesis constraints for the blocks / subsystem Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation What You'll Need: Education: Bachelor's or master's degree in electrical or Electronics and Communication or Computer Science Engineering. Experience: 8+ years of proven experience in SoC architecture, development, and full-chip design for multi-million gate SoCs. Expertise: Strong understanding of the design convergence cycle, including architecture, micro-architecture, verification, synthesis and timing closure. Expertise in managing IP dependencies, as well as planning and tracking front-end design tasks. Ability to drive project milestones across design, verification, and physical implementation phases. Experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains is highly desirable. Skills: Excellent communication and interpersonal skills. Ability to collaborate in a fast-paced, product-oriented, and distributed team environment. Minimum Qualifications: SoC Design Experience: Minimum 8+ years of hands-on experience in SoC design. Architecture Development: Ability to develop architecture and micro-architecture based on specifications. Bus Protocols & Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc. Memory Controllers & Microprocessors: Experience with memory controller designs and microprocessors is an advantage. Chip IO Design: Knowledge of chip IO design and packaging is beneficial. Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics. Synthesis & Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC. Timing Closure: Comprehensive understanding of timing closure is mandatory. Post-Silicon Debug: Experience in post-silicon bring-up and debugging. Decision Making: Ability to make effective decisions under incomplete information. Communication & Leadership: Strong leadership and communication skills to ensure effective program execution. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Great compensation package Restricted Stock Units (RSUs) Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

Position: ASIC RTL Design Lead (SI90FT RM 3217) Job Description: Innovate, implement, and verify RTL code for complex PHY sub systems dealing with high speed blocks using Verilog/System Verilog knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must. Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution Previous experience with storage systems, protocols, in NAND flash /DRAM controller PHY Basic understanding of PHY system level concepts Experience in PHY architecture, power management and Registers understanding to interact with FW design. Proficient in C, C++, Lint Excellent interpersonal skills and Team Player High level of integrity and commitment to quality and timeliness. Understanding of Hardware Block Diagrams, Schematics Understanding of PHY Architecture document and programming guidelines Understanding of PHY integration guidelines implementation Strong can-do attitude Job Category: Embedded HW_SW Job Type: Full Time Job Location: Bangalore Experience: 9+ YEARS Notice period: 0-30 days

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Sr Engineer, Digital Design Job Description Design key digital blocks such as clocks, reset paths, memory controller, NVMs etc. in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs Develop strong understanding of ARM processor cores subsystems (M series associated infrastructure such as caches, interconnect fabric, DMA, MMU, Coresight Debug Trace, TZC) and their integration requirements Design for Test skills on SCAN, MBIST boundary scan, JTAG and ARM DAP interface and general functional DFT understanding. Experience of AFE based projects is an add on. Package Digital IP for seamless integration into design flow at different stages - RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc. Consolidate curate digital IP for SPI/ I2C/ UART/ JTAG and other slow serial interfaces peripherals ATPG vectors, MBIST and BSCAN post silicon debug support. Develop User Guides for RTL Integration, Synthesis, DFT, PnR, Programming Sequence, characterization etc. Minimum Qualifications Minimum B.E. / B.Tech degree in Electrical/Electronics/Computer science 4 - 8 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis Good interpersonal, teamwork and communication skills to logically effectively drive discussions with teams spread geographically Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus Experience with end-to-end ASIC/ SoC product development productization is very desirable Experience in IP integration (memories, IO s, embedded processors, hard macros, Analog IP) Knowledge of Microelectronics concepts Scripting skills in Python, Tcl, C etc Ability to collaborate and work directly with the tool vendors to resolve tools bugs, as well as implement the required improvements Great communication and teamwork skills

PCB Design Engineer Work Location: Mysore, India Experience Required: 10+ Years Notice Period: Immediate to 15 days Mandatory skills for the requirement - Altium Minimum of 10 years of experience in PCB design and schematic capture with expertise in Altium Designer. Strong understanding of Analog and Digital circuit design. Experience in high-speed PCB routing and signal integrity analysis. Knowledge of EMI/EMC guidelines for PCB design. Familiarity with IEC 60601-1 and IEC 60601-1-2 standards Experience with cable assembly drawings in Altium designer. Ability to interact with PCB/PCBA manufacturers and suppliers to resolve technical issues. Knowledge of DFM (Design for Manufacturability), DFT (Design for Testability), and DFA (Design for Assembly) principles. Knowledge of thermal management techniques in PCB design Strong analytical, troubleshooting, and problem-solving skills. Excellent communication and teamwork skills. Interested or know someone perfect? Please send your resume or refer talented friends to hr@aadhyarajtech.com or contact via LinkedIn. Your referral could help a great professional find an exciting new opportunity! Show more Show less

Job Opportunity: Seeking highly motivated, energetic, team-oriented Individual Contributor driving roadmaps for IP / SS domain including complete IP portfolio, going deeper into logic design and architecting and developing Complex IPs / Subsystems solutions. Working closely with experienced and motivated team of Global experts in Systems, SoC Design functions to address the design/architectural challenges in the context of the complex IP and overall System level solutions. Work through a wide spectrum of skill from developing High level Specifications to actual design Implementation. Key Responsibilities Own and drive Roadmaps for complete IP / Subsystem domains portfolio within global R&D team. Perform benchmarks against other industry players and ensure differentiating features for our customer with high level of innovation. Architect and Design complex IP and Subsystems across a range of protocols required for Automotive Self Driving Vehicles (ADAS) both Vision and Radar, In-Vehicle networks, Gateway Systems, Fail Safe Subsystems (ASIL-D) etc. Own and Lead IP / Subsystem from Concept till IP Design and Development achieving final design performance in integrated system within aggressive, market driven schedules. Ensure quality adherence during all stages of the IP development cycle and carry out a thorough analysis of existing processes, recommend and implement the process improvements to ensure ‘Zero Defect’ designs and drive and mentor teams towards that. Key Skills Self starter with 10-14 years of hands-on experience to Architect and Design complex IP design / Sub-system with minimal supervision. Custom Processor Designs with key DSP functions like those needed for Vision and Radar processing. Experience in High Speed Serial protocols and associated high speed challenges on controller and PHY for PCIe, Ethernet & MIPI CSI2. Understanding of key External Memory interface protocols including DDR4 / LPDDR4, QuadSPI Flash interfaces. Experience in microcontroller architecture, Cache, protocols like AHB/AMBA,AXI. Extensive hands on knowledge of HDLs (Verilog/VHDL), Scripting languages (Perl, Tcl), C/C++ for hardware modeling. Understanding of end to end IP development flow including complex CDC, RDC constructs, IP Synthesis, DFT ATPG coverage. Have worked on Testbench and Testplan development closely with the verification team. Hands on work on pre silicon validation using FPGA/Emulation Board would be a significant added advantage. Key Soft Skills Proficient skills in both written and verbal communication. Can articulate well. Has a sense of Ownership and engages everyone with Trust and Respect. Should demonstrate Emotional Intelligence and Leadership values with ability to work well as a part of team both local and remote or multisite. More information about NXP in India... Show more Show less

Key Information Location : Embassy 247 IT Park, Vikhroli, Mumbai. Workplace type : Hybrid. Experience level : 6-8 years. Core Skills : Technical Product management for IoT/Smart Sensor domain. About Freespace (afreespace.com) We're a workplace technology company helping organizations to achieve three key outcomes : Right size, right design : Enabling informed decisions using real-time data to achieve portfolio optimization and the right workplace design. Smart building automations : Streamlining processes by simplifying complex seating requirements and through occupancy-driven control and automation. Exceptional employee experiences : Maximizing the benefits of the office by providing employees with the tools to find and reserve spaces, connect with each other and enjoy optimal working conditions. To achieve these outcomes, we provide an integrated platform that delivers actionable workplace intelligence, through a real-time analytics platform, workplace sensors, employee experience app, signage and space management solutions. We have recently been recognized with a nomination for the IFMA New York Awards of Excellence in the Sustainability category, underscoring their achievements in fostering adaptive, efficient, and sustainable work environments. About Role As a Technical Product Owner for the Smart Buildings team, you will play a key supporting role to the Product Manager, ensuring that the product vision and roadmap for our sensor and automation solutions are clearly translated and aligned with engineering teams. You will contribute to the development and be responsible for tactical execution-managing the product backlog, defining user stories, and ensuring technical requirements are met. Your role is pivotal in bridging business objectives with technical delivery, ensuring the successful implementation of smart building products. Key Responsibilities Collaborate closely with the Product Manager to understand and contribute to the product vision, strategy, and roadmap for smart building hardware and automation solutions. Translate high-level product goals and features into actionable user stories, technical requirements, and acceptance criteria for the engineering teams. Create, refine, and prioritize the product backlog, ensuring clarity and alignment with both business objectives and technical feasibility. Serve as the primary liaison between the Product Manager, Business Analyst, and engineering teams, facilitating clear communication and resolving ambiguities in requirements. Support sprint planning, backlog grooming, and release planning in coordination with the Technical Project Manager (TPM) to ensure timely and high-quality delivery. Monitor progress, remove blockers for the engineering team, and provide ongoing support to ensure features are delivered as intended. Ensure developed solutions meet acceptance criteria and are aligned with client needs and the overall product vision. Gather feedback from stakeholders, analyze product performance data, and recommend improvements for future iterations. Stay informed about industry trends in smart building technology, IoT sensors, and automation to inform backlog priorities and technical decisions. Collaborate with Operations and Support teams to address technical issues and ensure smooth product onboarding and customer satisfaction. Required Skills & Experience 5+ years' experience in Agile Scrum environments, ideally as a Product Owner or Business Analyst in technology or platform-focused teams. Deep technical understanding of IoT sensor hardware, including :. Circuit Design and hardware technologies (e.g, microcontrollers, thermal imaging sensors, analog/digital signal processing). Lower-level algorithmic understanding for sensor data acquisition, filtering, and calibration. Ability to read and understand firmware coding languages such as C, Python, Squirrel, and familiarity with embedded software development and debugging. Good understanding of manufacturing and factory processes, including :. Design for manufacturability (DFM) and design for testability (DFT). Familiarity with PCB assembly, SMT processes, and end-of-line testing. Experience working with contract manufacturers, understanding of quality control, yield improvement, and root cause analysis for hardware issues. Experience driving device testing : Parametric testing (electrical, thermal, mechanical parameters). Field testing and simulation set-ups to validate device performance under real-world and edge-case scenarios. Ability to define test cases and acceptance criteria for hardware and firmware validation. Understanding of cloud data pipeline technologies used for device data reporting and analytics, including data ingestion, transformation, and storage (e.g, AWS IoT, Azure IoT Hub, MQTT, REST APIs). Knowledge of LoRaWAN and other wireless communication protocols relevant to smart building sensor networks. Familiarity with building automation systems and integration protocols (e.g, BACnet, ModBus, KNX). Proven ability to translate business requirements into actionable user stories and technical tasks for hardware and software teams. Excellent communication and stakeholder management skills, with the ability to bridge gaps between business and engineering teams. Strong analytical and problem-solving skills, with attention to detail and a proactive approach to identifying and resolving issues. Self-motivated, adaptable, and able to manage multiple priorities in a fast-paced environment. MBA or equivalent business qualification is preferred. Additional Technical Skills (Preferred) Experience with sensor calibration, environmental testing, and compliance standards (e.g, CE, FCC). Familiarity with device provisioning, OTA firmware updates, and device lifecycle management. Exposure to cybersecurity concepts as they relate to IoT devices and data privacy. Behaviours & Mindset Solution-oriented and curious, with a drive to understand and solve technical challenges. Collaborative and inclusive, fostering teamwork across functions. Highly organized, detail-focused, and able to manage competing priorities effectively. Clear communicator, able to simplify complex technical concepts for diverse audiences. Why Join Freespace Smart Buildings ? Work at the forefront of smart building innovation, shaping sensor and automation solutions that transform workplaces. Collaborate with a passionate, entrepreneurial team driving real-world impact. Hybrid working flexibility and a supportive culture focused on career growth and continuous learning. Competitive benefits, including paid leave, health coverage, bonus schemes, and funded training. (ref:hirist.tech) Show more Show less

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels. Available Job Responsibilities Design and build memory or circuit blocks at the gate or transistor level Simulate and analyze the circuit design using transistor level simulators Extract the layout and perform post-layout simulations and verification Floorplan physical implementation and layout integration of design components Integrate characterization flow to extract timing and power information Develop scripts to automate characterization flow, simulations, and verification Specify and verify various behavioral and physical memory models Document the design specifications, behavioral description, and timing diagrams Help specify silicon test plan and correlate silicon to simulation data Preferred Skills Good understanding of transistor level circuit behavior and device physics Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis Proficiency in running simulators, writing automation scripts, and are tools savvy Understanding of memory behavioral and physical models is a plus Expertise in memory circuit design is a plus Understanding of DFT schemes and chip level integration is a plus Good communication, interpersonal, and leadership skills Motivated, self-driven and good at multi-tasking Passion for solving complex problems and willingness to learn

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the development of foundation IP for AI products including memory compilers, logic cells and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels. Available Job Responsibilities Design and build memory or circuit blocks at the gate or transistor level Simulate and analyze the circuit design using transistor level simulators Extract the layout and perform post-layout simulations and verification Floorplan physical implementation and layout integration of design components Integrate characterization flow to extract timing and power information Develop scripts to automate characterization flow, simulations, and verification Specify and verify various behavioral and physical memory models Document the design specifications, behavioral description, and timing diagrams Help specify silicon test plan and correlate silicon to simulation data Preferred Skills Good understanding of transistor level circuit behavior and device physics Good understanding of signal integrity analysis, EM/IR analysis, and reliability analysis Proficiency in running simulators, writing automation scripts, and are tools savvy Understanding of memory behavioral and physical models is a plus Expertise in memory circuit design is a plus Understanding of DFT schemes and chip level integration is a plus Good communication, interpersonal, and leadership skills Motivated, self-driven and good at multi-tasking Passion for solving complex problems and willingness to learn .

Broadcoms Central Engineering Group (CEG) is looking for an experienced, energetic and self-driven professional to join our team as a senior modeling engineer for the development and improvement of functional, timing, power, and DFT simulation models. This role will focus on authoring, debugging, and optimizing memory IP (SRAM, RF, CAM, ROM, etc.) EDA models used in ASIC-like design flows by chip teams throughout the company. This is a senior position with the expectation that the candidate can lead projects, proactively navigate complex technical issues, be able to work autonomously, and collaboratively participate in the establishment of strategic objectives. The candidate must have abilities to prioritize well, communicate clearly and concisely, deliver high quality solutions on-time, and possess excellent problem solving skills. This person will be expected to work across multiple facets of projects, have experience with ASIC development, and juggle multiple responsibilities at the same time exhibit excellent multitasking, context switching, and time management skills. Responsibilities: Candidate will Lead memory modeling and compiler development projects working closely with design teams in an environment highly charged with technical complexities and dynamic schedule challenges. Be expected to demonstrate skills and abilities to lead and drive results improvements, multitask and deliver high quality solutions in a timely fashion. Write model templates for integration into memory compilers to generate models used in DFT/CAD tools used in ASIC development flows. Participate in forums for model development, improvement and reviews, and will serve as a knowledge resource for peers, colleagues, and subordinates in the organization. Be expected to communicate well, document well, prioritize tasks and handle the multiple facets of model development projects independently to meet the business goals and commitments. Work to improve memory models and model generation flows for better performance, user experience and quality. Work directly with IP design teams, compiler teams and tool vendors globally to help resolve model related issues, and find timely solutions. Respond to library support requests and address tickets on model issues from product teams across Broadcom. Qualifications : The minimum engineering experience required is typically a BS degree in EE/CS/CE with programming/coding experience with 8+ years of industry experience, or an MS degree with 6+ or Ph.D. degree in EE/CS with 3+ years of industry experience. Have at least 3 years experience using Linux systems; possess excellent knowledge of Linux commands, file systems, and job execution. Strong preference for 5+ years of experience in Verilog modeling skills Static Dynamic timing analysis knowledge. Experience with chip design tools and design flows, such as: DFT: Tessent, LogicVision, Modus, manufacturing test flows: at-speed scan test, Logic BIST, Memory BIST Synthesis: Design Compiler, Genus. Simulation: VCS, Questa, Verilog, waveform viewers, and simulation debug. STA: Primetime, Tempus, Celtic, Velocity. Power Analysis: Redhawk, Voltus, PowerCompiler, Power Artist. PR: ICC, Innovus, Olympus, Encounter. Conversant with Verilog / RTL / Behavioral / Timing / Power / DFT / ATPG / Synthesizable model development for SRAMs/RF/CAM/ROM, etc. memories. Experience in writing directed test bench in verilog for model verification. Knowledge and experience using simulators - NC, VCS, ModelSim, ESPCV is a must. Familiarity with memory model verification/QC flow is required. Scripting flow automation, Perl, Python, Tcl, Shell programming skills are required. Able to work in agile and dynamic development environments. Excellent written and verbal communication skills. Skilled multi-tasking abilities and context switching skills are a must. Strong analytical, problem solving and quick learning skills are required. Good team player, methodical, eye for detail, independent, well organized, and have the ability to remain calm and composed in high pressure situations. .

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design and implement a full, dedicated, and flexible (e.g., UVM based) verification environment Involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of the overall system-level solution. Defining verification strategy from IP to top digital integration Define requirements for block level and full-chip level verification infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Debug failures and drive in-time resolution of bugs Create coverage monitors and drive coverage to required quality targets Develop tools, test benches, and test suites (UVM, C++/C ) to execute test plans. Write functional coverage, analyze both code and functional coverage, and close coverage gaps Develop and use unit level test benches that use functional tests as well as constrained random stimulus. When needed, define and develop formal verification environment Skills BS or MS in EE, CS or related engineering discipline 5-10 years of demonstrated experience in verification of IPs, Digital Design and SoCs Strong experience in design and verification standards and methodologies (SVA, UVM/OVM). In-depth knowledge of Verilog and System Verilog HDL and experience with simulators and waveform debugging tools Solid understanding and experience with verification of Digital Design and SoC architectures including test planning, constrained random test generation, test stimulus, code coverage, functional coverage. A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis and closure). Strong experience creating test benches and automating regression test suites, preparing, and presenting detailed verification reviews Knowledge of state-of-the-art EDA tools (e.g., Cadence Xcelium…) Experience with formal verification is plus. Programming experience in languages common to the industry (e.g., C, C++, Shell scripting) Solid scripting skills (Python preferred or Perl or TCL). Knowledge of test and DFT (Scan insertion, Scan compression, test coverage analysis, ATPG pattern generation, simulation and debug, IEEE 1149.1, 1500 and 1687 standards) We’re doing work that matters. Help us solve what others can’t. Show more Show less