1121 Dft Jobs - Page 38

You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces . You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards , and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure , sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You'll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage , and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You'll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities.

Who We Are Amchem is one of the leading two-component polyurethane coating manufacturers in the world. We have been in business for over 30+ years and have worked with some of the Worlds biggest pipe manufacturers such as Jindal Saw LLC, Welspun, Oriental Steel, Electrosteel etc. on projects totaling over 75 million square feet. We are growing at more than 50% CAGR and have been recently awarded “Star Export House” by the Government of India. With our new line of products that meet industrial standards from all over the world (USA – AWWA C222, France – ACS, UK – WRAS, Europe – EN 10290 / 15655 / 15189, etc.), we are looking to expand more aggressively into newer markets. What We Offer At Amchem Products, we are committed to creating high-quality polyurethane coatings that exceed customer expectations. We aim to foster a culture of innovation, collaboration, learning, and especially ownership. We believe every employee should have ownership over their work such that they can feel empowered to challenge and improve systems and processes that dictate our direction. Benefits We offer a comprehensive benefits package that includes: Competitive pay (let’s talk!) Health insurance including medical, dental, vision, etc. (group insurance for your family) Contribution to Provident fund Yearly bonus (equivalent to at least 1 month of your basic salary) Paid Time Off (23 days per year) Paid Sick Leave (7 days per year) Cafeteria (free coffee, snacks, etc.) Opportunities for travel, professional trainings, and growth Requirements: Education: Diploma/Degree in Mechanical Engineering, Chemical Engineering, or equivalent. Skills: Strong communication skills. Knowledge of coating systems, procedures, and testing. Ability to work under high pressure, in isolation, or in challenging terrains/climates. Familiar with health, safety, and environmental (HSE) protocols. Physically fit and medically cleared for harsh environments. Your Responsibilities Supervise and coordinate all pipeline coating activities on international project sites, including remote deserts, offshore platforms, and cold-weather regions. Ensure proper surface preparation, coating application, curing, and inspection. Lead a team of coating technicians, helpers, and subcontractors with a focus on productivity and safety. Ensure all coating works meet industry standards or project-specific requirements. Verify materials, equipment, and environmental conditions prior to coating operations. Monitor weather, humidity, temperature, and other site conditions affecting coating quality. Prepare and maintain daily progress reports, manpower reports, and site diaries. Manage emergency response protocols and adapt plans during hazardous weather or worksite risks. Ensure equipment maintenance and calibration (e.g., holiday detectors, DFT gauges, etc.) is up to date. Participate in internal and external audits and ensure documentation is complete and accurate. Extended shifts (up to 12 hours/day) in environments with extreme temperatures, wind, noise, and dust exposure. If interested either apply through LinkedIn or reach out to staffing@amchemproducts.com with a copy of your resume. We will reach out to you shortly thereafter! Show more Show less

To work as a Frontend Lead and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects. Job Description In your new role you will: Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirements. Your Profile You are best equipped for this task if you have: Strong fundamentals and experience in Synthesis and STA domains. Write and implement block level and top-level timing constraints for Synthesis Optimize designs for power, performance, and area, and meet design goals. Knowledge on Power analysis and PT-PX flow. Understanding of DFT flows, including scan insertion. Write and evaluate Test/DFT mode timing constraints. Thorough with Logic Equivalence Check debug capability. Well known about UPF concepts and Low Power Checks at block and full chip level. Defining and verification of STA constraint for Functional and Test/SCAN Modes. Defining PVT’s corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues. VASTA timing closure based on chip IR drop. Knowledge on signal SI analysis and PT-PX flow. . Contact: Swati.Gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

The Group You’ll Be A Part Of In the Global Products Group, we are dedicated to excellence in the design and engineering of Lam's etch and deposition products. We drive innovation to ensure our cutting-edge solutions are helping to solve the biggest challenges in the semiconductor industry. The Impact You’ll Make As a Mechanical Engineer at Lam, you're designing and defining cutting-edge mechanical and electro-mechanical systems. Your role involves feasibility studies, testing, and guiding teams in detailed design and fabrication. You provide the crucial design information needed to shape our technology's packaging. In this role, you will directly contribute to ___. What You’ll Do Primary Responsibilities: Conceptualizing, Designing, developing and implementing cost-effective design solution for power distribution systems and power boxes Reviewing, validating and selecting OEM components – Circuit Breakers, Interlocks, Mechanical Hardware, Busbars (rigid and flexible), Door Hinges and latches, cable tracks, cooling fans, door gaskets, weldment studs, structural fasteners, conduits, clips, eye bolts etc. Designing sheet metal enclosures and materials for power boxes Reviewing and approving engineering drawings & bill of materials using Engineering Change Management process Leading Interactions with PG counterpart in US Studying and recommending corrective solutions for Problem Reports of varying complexities on power boxes from suppliers and customers. Provide immediate response and timely resolution to design related production issues encountered during the first build process Peer Reviewing Power Box designs, conducting design review to get buy-in from all cross functional teams (primarily Electrical Engineering Team) Developing Processes, Best Practices for Mechanical Engineering for Power Box Designs Focusing on Quality Improvements for ME Power Box Designs (Implementation of DMADV or any such methods) Driving DFMEA, DFR, DFT, DFS, DFM, DFC Driving Continuous Improvement and Innovation Projects Experience with harness routing & documentation for Power Boxes Managing in a very dynamic and fast paced work environment with frequent updates, design packages with quick solutions etc. Who We’re Looking For Mandatory Skills required to perform the job: Educational Qualification: B.E/B.Tech or M.E/M.Tech (Mechanical) Years of experience: 12+ years of relevant experience Proficiency in design of Power box / control panels /electro mechanical boxes Proficiency in designing complex sheet metal structures and release of manufacturing drawings Proficiency in Thermal hand calculations and basic simulations (Conduction, Convection, Heat dissipation and increase in temperature) to facilitate selection of heat sinks, Cooling systems like Fans, Component Layouts, Louvers etc. Proficient in 3D Modelling, Assembly and Detailing using Nx or CREO & PLM, PDM Advanced structural calculation’s & simulations - consideration of serviceability and facia design (outer panels) – Door, Access Panel, LOTO, Door Hinge design with Interlock, Busbar Strong knowledge of GD&T application Strong knowhow of welding Proficiency on SEMI standards - implementation experience Structured PS&DM experience – PB level issues. Proficient in Designing for cost targets, optimization of design footprints etc. Experience on coatings and finishes Experience with plastic components, elastomers and viewports, associated flammability standards Detailed knowledge of typical Power box issues in the field Exposure to Value Engineering would be an advantage Independently managing with projects/tasks and ability to prepare documents with MS Office Preferred Qualifications Desirable Skill: Detailed knowledge on analysis software’s like Nx-Nastran to validate the design Exposure to knowledge on schematics and electrical components (CB, Contactors, SSRs, switching power supply etc.) and 480V AC/208 V AC electrical components Knowledge in Engineering Change Management Process Exposure to Value Engineering would be an advantage Awareness on EMC & EMI requirements Exposure to Seismic Analysis, Vibration Analysis Functional testing experience Our Commitment We believe it is important for every person to feel valued, included, and empowered to achieve their full potential. By bringing unique individuals and viewpoints together, we achieve extraordinary results. Lam Research ("Lam" or the "Company") is an equal opportunity employer. Lam is committed to and reaffirms support of equal opportunity in employment and non-discrimination in employment policies, practices and procedures on the basis of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex (including pregnancy, childbirth and related medical conditions), gender, gender identity, gender expression, age, sexual orientation, or military and veteran status or any other category protected by applicable federal, state, or local laws. It is the Company's intention to comply with all applicable laws and regulations. Company policy prohibits unlawful discrimination against applicants or employees. Lam offers a variety of work location models based on the needs of each role. Our hybrid roles combine the benefits of on-site collaboration with colleagues and the flexibility to work remotely and fall into two categories – On-site Flex and Virtual Flex. ‘On-site Flex’ you’ll work 3+ days per week on-site at a Lam or customer/supplier location, with the opportunity to work remotely for the balance of the week. ‘Virtual Flex’ you’ll work 1-2 days per week on-site at a Lam or customer/supplier location, and remotely the rest of the time. Show more Show less

Eligibility Criteria Educational qualification: Bachelor of Electrical/Electronics Engineering, MTech is an added advantage. Years of Experience: 4+ years of relevant experience in schematic & PCB design & testing, cable design Primary Responsibility Responsible for executing Electrical Engineering technical disciplines with primary focus on designing and modifying schematic and PCB layout. Board Design, Electronics Circuits including microcontroller/FPGA based designs, sensor interfaces, analog signal conditioning circuits, power supplies, ethernet based communication interfaces, Wireless Interfaces, Wireless Chargers etc. Creation of system interconnects diagram and electrical schematics diagram based on requirements received from cross-disciplinary teams Own the Cable Designs, drafting of cables, creation of harness drawings Work with cross-disciplinary teams (including mechanical, electro-mechanical, software, process, manufacturing engineers) for major projects with multi-national work environment. Creating electrical schematics and PCB layouts based on requirements received from cross-disciplinary teams Creating and releasing engineering drawings & bill of materials using Engineering Change Management process Interacting with PG counterpart in US Studying and recommending corrective solutions for technical issues of varying complexities. Conducting Design review to get buy-in from all cross functional teams Managing in a very dynamic and fast paced work environment with frequent updates, design packages with quick solutions etc. Mandatory Skills Required To Perform The Job Core PCB Design Expertise with OrCAD Allegro – designed complex boards 10-12 layers with SMD’s, BGA’s, through hole parts, placement, routing, setting up constraints, working with component library teams for PCB footprint Performing Schematic Entry in OrCAD Design Entry and circuit understanding with op-amps, comparators, passive devices, sensor circuitry, semiconductors IC’s – microcontrollers/FPGA, power supplies (DC-DC Converters) Working alongside EE, ME for planning the board, DFT philosophy, working with PCB vendors for design for manufacturability (DFM), mechanical packaging constraints and PCB stack-up Ability to write test plans for PCB testing and ability to perform low level IO testing on sub-controller and devices, debugging board failures/issues Creation of electrical schematic diagram for cables, knowledge of Zuken Semiconductor domain knowledge would be a value addition Our Commitment We believe it is important for every person to feel valued, included, and empowered to achieve their full potential. By bringing unique individuals and viewpoints together, we achieve extraordinary results. Lam Research ("Lam" or the "Company") is an equal opportunity employer. Lam is committed to and reaffirms support of equal opportunity in employment and non-discrimination in employment policies, practices and procedures on the basis of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex (including pregnancy, childbirth and related medical conditions), gender, gender identity, gender expression, age, sexual orientation, or military and veteran status or any other category protected by applicable federal, state, or local laws. It is the Company's intention to comply with all applicable laws and regulations. Company policy prohibits unlawful discrimination against applicants or employees. Lam offers a variety of work location models based on the needs of each role. Our hybrid roles combine the benefits of on-site collaboration with colleagues and the flexibility to work remotely and fall into two categories – On-site Flex and Virtual Flex. ‘On-site Flex’ you’ll work 3+ days per week on-site at a Lam or customer/supplier location, with the opportunity to work remotely for the balance of the week. ‘Virtual Flex’ you’ll work 1-2 days per week on-site at a Lam or customer/supplier location, and remotely the rest of the time. Show more Show less

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Design Verification Engineer, you will work with a highly innovative and motivated design and verification team using state of the art memory technologies to develop the most advanced DRAM and Emerging memory products. You will be challenged by the complexity and difficulty of verifying high density memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors), ultra-high speed designs, complex functionality which includes next Generation DDR/LPDDR (ex: DDR6, DDR5, LPDDR6, LPDDR5, HBM) and advanced low power and power management technologies. You will be responsible to evaluate the functionality and performance of the Full-chip and block-level circuit designs using different verification tools, techniques, and strategies. In addition, you will also need to provide solutions to help deliver a functionally correct design. Lastly, you will need to collaborate closely with Micron's various design, verification, and product engineering teams all over the world to ensure design project success. What’s Encouraged Daily Develop verification infrastructure and environment to verify probe and burn DFT testmodes functionality. Develop verification infrastructure and environment to port-over the probe and burn DFT patterns into the digital desing verification flow. Provide verification support to the DRAM and Emerging Memory Design Engineering teams by simulating, analyzing, and debugging pre-silicon full-chip and block-level designs. Develop SystemVerilog testbench infrastructure (e.g. UVM/Non-UVM and Constrained Random Verification Methodology) Responsible for test plan execution, running regressions, code and functional coverage closure Assist product engineering teams with circuit and simulation support during post-silicon validation phase. Analyze gaps within the verification flow and methodology and provide solutions to address them. Develop, run, and maintain verification test benches and vectors using industry standard and inhouse developed programs. Write test patterns/vectors and monitors to enhance the functional coverage for all DRAM and Emerging Memory architectures and features. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. Show more Show less

What You ll Need: BSEE or MSEE with a minimum of 4 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying verilog and system verilog design. Experience of working with minimum supervision and owning and delivering for Front end activities in IP/SOC Experience of leading technically for Front end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred).

What You ll Need: BSEE or MSEE with a minimum of 4 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying verilog and system verilog design. Experience of working with minimum supervision and owning and delivering for Front end activities in IP/SOC Experience of leading technically for Front end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred).

Chip Lead (Sr Mgr/Director) Hyderabad A Hyderabad based SoC product design company is looking for a talented, energetic and diligent SoC Director for leading the development of a new generation of devices. Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs in the area of HBM. Job responsibilities include: Driving the specification of the chip with architect and design leads – eventually cascading into block specifications. Make PPA decisions for the chip. Defining multiple development checkpoints – for IP/SoC Design/DV/PD Come up with overall project plan and cascaded schedule details for other teams Work with Analog/Digital IP teams to laydown integration details for the IPs. Drive the full chip floorplan / bump maps and provide area/floorplan targets to IP teams. Define the sign-off criteria for the device. Define the SoC verification plan items/scenarios to be covered. Assist/Review the micro architecture definition for digital blocks Define RTL Quality gate criteria for integration – Lint/CDC/ Drive the timing constraints/timing analysis/closure activities. Define the DFT targets for the chip and cascade that into activities needed on the DFT front. Work with PD enginers to get the physical design closure. Handle tapeout formalities Qualifications: Close to 15 years of solid experience in SoC design. A self starter. Candidate ready to define things where none exist. Ready for once in a lifetime project exposure, but ready to do heavy lifting for the effort. Proven ability to develop architecture and micro-architecture from specifications. Understanding of chip I/O design and packaging is advantageous. Experience in reviewing top-level test plans. Expertise in Synopsys Design Compiler for synthesis and formal verification. Strong working knowledge of timing closure processes. Experience with post-silicon bring-up and debugging. Familiarity with SoC integration challenges. Knowledge of design verification aspects is essential. Experience from SoC specification to GDS and commercialization is highly desired. Ability to make timely and effective decisions, even with incomplete information. Demonstrated expertise in specific technical areas, with significant experience in related fields. Provide direction, mentoring, and leadership to small to medium-sized teams. Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

What You ll Need: 0-3 years of related experience in DFT architectures and methodologies. Moderate experience in generating scan patterns and coverage statistics for various fault models. Experience in scan stuck-at and at-speed coverage exploration, simulation, and debug. Familiarity with state-of-the-art EDA tools for DFT, design, and verification. Basic knowledge of STA for DFT mode timing constraint development and exploration. Who You Are: Excellent communicator with the ability to work effectively with cross-functional teams. Detail-oriented and driven by a passion for technology and continuous learning. Strong debugging skills and experience in scripting languages like Perl, TCL, and Python. Committed to fostering an inclusive and diverse work environment. Adaptable and eager to take on new challenges and responsibilities.

Sr Engineer/ Lead Engineer - Power Electronics Experience : 6 - 10 Years Location : Ernakulam, Kerala Job Description Required Skills: Manage Power converter design and development projects hardware like AC to DC, PFC, DC to DC, DC to AC from few watts to around 50KW range Ability to drive technically and has rich experience in all stages of project development lifecycle Experience in different Topologies for Power conversion Hands-on experience in Power converter designs like Topology selection, schematics preparation, component selection, PCB design guidance etc. Experience in Low or High Power Board bring up & Functional testing. knowledge on Magnetics design and construction methodstool (Xpedition, Allegro, Orcad, PADS etc.) knowledge on Magnetics design and construction methods Hands on experience in pre-compliance and compliance testing Experience in preparation of design documentation such as Loss calculations, test plan and detailed design specification, derating, FMEA, Reliability, MTBF Exposure to hardware tools ( Energy / Power Analysers , Oscilloscopes, Electronic loads, Function generator) Ability to work in a diverse, cross-functional team Knowledge of Design for excellence viz. DFT, DFM, DFA Excellent written and oral communication skill Qualification: Graduation/Post graduation in Electrical & Electronics / Power Electronics or equivalent Show more Show less

Greeting with HCL Tech! We were looking somebody who is having experience in DFT Experience: 4 to 10 Years Location: Kochi Hands-on experience with Scan, EDT, SSN insertion, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing. Hands-on Experience to do MBIST Insertion, Verification including Repair mode, Pattern generation. Spy Glass experience to resolve DFT DRC at RTL stage. SoC Translation flow, Patterns hand-off. Post Silicon Debug on Tester. Strong co-working experience with other dependent functions, Constraints development, STA & Physical Design. Should be able to handle team of 4-6 members. Drive team towards meeting Milestone in high pressure situation. Added advantage if Lead has executed 2-3 Projects in Intel flow.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years’ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG In depth knowledge of DFT concepts. In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. Expertise in scripting languages such as perl, shell, etc. Experience in simulating test vectors. Knowledge of equivalence check and RTL lint tool (like spyglass). Ability to work in an international team, dynamic environment Ability to learn and adapt to new tools and methodologies. Ability to do multi-tasking & work on several high priority designs in parallel. Excellent problem-solving skills Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076092 Show more Show less

Introduction As a Hardware Developer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in todays market. Your Role and Responsibilities : We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Your role and responsibilities We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.Proven expertise in analysing and resolving DRCs/TSVs .Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .Hands on experience on industry standard tools used for DFT featuresProficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.Excellent analytical and problem-solving skills, with a keen attention to detail.Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design . Experience working with ATE engineers for silicon bring up, silicon debug and validation. . Experience in processor flow and post silicon validation Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role Our Physical Design Implementation Engineer will work with multi-functional global teams to implement Partition/Block level Synthesis, Floorplan, Place and Route, Timing closure, IR/EM and DRC/LVS closure for our next generation highly complex 5nm/3nm/advanced-node Server class Processor products. PD work at Ampere is interesting, challenging, and will expand your professional breadth. We like to bring out the best in people, teach each other, and produce products that have value in the market. In this role, you will be at the forefront of our groundbreaking AI compute solution. Our products combine high-performance general-purpose CPUs with AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. What You’ll Achieve As a member of the PD Team, you will plan and implement a significant portion of the Chip Layout partnering with design and DFT engineering peers. You will create solutions to meet challenging frequency, power, area, clocking and design partition goals. You’ll get to work with custom and tool-driven CTS and physical design integration methodologies. About You B.Tech in Electronics Engineering or Computer Engineering with 3-5 years of semiconductor experience, or M.Tech with 2-4 years of experience. Good knowledge of EDA tools from Synopsys or Cadence or Mentor required. In particular experience with PTSI, Innovus, Calibre, StarRC, and Conformal LEC is essential. Good knowledge of VLSI process and device characteristics, to make optimal trade-off between performance and power. Good understanding of static timing analysis (STA), EM/IR and sign-off flows. Expertise in physical design of high frequency chips with emphasis on successful timing closure. Good understanding of physical design verification. Experience in implementation and design closure with advanced process nodes like 5nm, 3nm etc. Strong Hands-on Experience With Floor planning, place & route, power and clock distribution, pin placement and timing analysis. Timing convergence using high speed design techniques with signal integrity & EM/IR. Good scripting skills (perl, python, tcl). Self-driven individual and an excellent team player experienced in working with remote teams. Must have good communication skills and the ability and desire to work as a team. What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law. Show more Show less

Work as a DFT Product Validation Engineer on insertion and validation of DFT technologies such as 1500 Wrapper, Compression, RTL DFT, Low Pin Count Test, Hierarchical Test, LBIST etc. using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer designs. Create testplans for verification of new features and execute them by creating new test cases requiring application of Design & DFT skills; Report bugs/enhancements in tool. Collaborate with R&D and Product Engineering teams to review feature specifications, testplans & customer issues. Debug issues reported by customers and suggest/implement measures to plug the gaps. Position Requirements B. E/B. Tech with 2+ years or M. E/MTech inElectronics/Electricalof experience Strong in Digital electronics, Verilog Good understanding of DFT techniques and methodologies Familiarity with Test standards like 1149. 1, 1500, 1687 is a plus Experience with Cadence Test or other Test tools is preferred Modus is a DFT (Design for Testability) software tool from Cadence used by leading chip design companies during DFT synthesis & ATPG (Automatic Test Pattern Generation) phase of chip design We re doing work that matters. Help us solve what others can t.

We are seeking a highly skilled and motivated STA Synthesis Engineer to join our offshore development teams . The ideal candidate will have expertise in static timing analysis (STA) to ensure the timing integrity of digital integrated circuits. Develop and execute timing constraints, ensuring compliance with design specifications and performance goals. Prepare detailed STA reports, including analysis and recommendations for improvements. Provide training and support to junior STA engineers and team members Role & Responsibilities : - Timing Constraint Generation : Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. - STA Setup : Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions. - Timing Analysis : Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). - Clock Domain Crossing ( CDC ) Analysis : Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues. - Multicycle Paths ( MCP ) and False Paths : Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints. - Timing Closure : Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues. - Clock Tree Synthesis ( CTS ) : Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter. - Post-Layout STA : Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure. - Timing Margins : Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation. - Report Generation : Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization. - Cross-Functional Collaboration : Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues. - Methodology Development : Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy. NOTE : Preferred resources holding valid regional work permits only

Job Opening for a Research Associate in Computational Materials Science/Chemistry, May 2025 Job Description (Research Associate) We are seeking a postdoctoral research fellow to join our team working on computational modelling novel catalysis and battery phenomena. The position will mainly focus on performing density functional theory (DFT) studies to identify potential catalyst materials relevant for sustainable water-splitting (OER, HER) and CO2 reduction processes and understand the reaction mechanism on solid catalyst surfaces. The postdoctoral fellow will collaborate closely with experimental scientists in RISE and work on defined areas required for the project. The candidate is also expected to have good knowledge about DFT studies of small molecules to obtain the structural and electronic properties. A candidate with previous knowledge on molecular dynamics studies is an added advantage and will be strongly favored. The candidate must hold, or soon obtain, a PhD degree within the field of computational chemistry, physics, materials science. Experience working in Linux computing environments, especially in the context of high-performance computing is mandatory. Working experience with some of the DFT programs like VASP, QuantumATK, Quantum Espresso, Gaussian are also mandatory. We expect the candidate to have good communication skills who can collaborate closely with other members of the research group as well as experimental group members of RISE. Screening of applicants will be based on previous experience followed by an interview. The position will be for one year initially, which can be renewed depending on the performance of the candidate. Interested candidates are requested to write to bidisa.das@tcgcrest.org Position: Research Associate Remuneration: Rs 58,000/- + HRA Duration: Initially for one year with possibilities of extension depending on performance. Last Date of Application : June 15, 2025 Essential Qualification PhD in Computational Chemistry / Physics / Materials Science. Benefits RISE offers competitive salary and have great opportunities of career growth and development. We have an excellent collaborative and supportive work environment and our research is primarily on translational projects which are being investigated by our experimental team. TCG CREST strongly encourages applications from women and less privileged groups under-represented in academia. Why TCG CREST? TCG CREST aspires to be a world-leading research institute that unleashes the untapped and true potential of human talent. As an institution, TCG CREST is especially dedicated to the three knowledge creation, knowledge application, and knowledge dissemination. The focus is on creating a strong network with highly-reputed knowledge centres worldwide: universities, research institutions, technology-driven global corporate entities, and academic communities. The goal is to inculcate a strong culture of continual knowledge exchange through research, student exchange, faculty exchange, joint projects, collaborative workshops, and participative seminars. TCG CREST is recognized as a Scientific and Industrial Research Organization (SIRO) by the Department of Scientific and Industrial (DSIR), Government of India. The AcSIR (Academy of Scientific & Innovative Research, Government of India) has recognized TCG CREST as its Associate Academic Centre. TCG CREST offers a unique working environment within the city of Kolkata. The Institute is situated on a beautiful urban campus in Sector V (the IT Hub), with easy access to a range of educational, cultural, and recreational activities. With its historical significance and landmarks, lively cultural offerings, and a wide variety of atmospheres, Kolkata is the perfect place to call home for study, work and play. Show more Show less

Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is alogic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Job Description In your new role you will: Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Candidate will be responsible for RTL design for integration of IO pads into SoC, building the required multiplexing logic and necessary powercontrol signals integration. Strong fundamentals in DFT/Fault-grading and/or hands on experience. Sound & Practical Written and Verbal Communication Skills. Your Profile You are best equipped for this task if you have: Must have worked in ASIC Design flow, with ASIC experience of upto 5years. Must be strong in scripting using Perl/Python Must be familiar with RTL design for ASIC development using Verilog. Must be familiar with LINT (LEDA / Spyglass) , Clock-Domain-Crossing analysis, UPF, MVRC, Synthesis , Timing constraints and debugging STAreports. Strong mindset towards automation of repetitive work. Strong fundamentals in DFT/Fault-grading and/or hands on experience. Sound & Practical Written and Verbal Communication Skills. Moderate Individual Contributor with Freedom to Act, Team work and Learn Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone.

Key Responsibilities Responsible for design and development of real time embedded software/firmware and PC/mobile based software application. To Analyse domain specific technical or low level requirement and modification as per end customer or system requirement. Participate in High level and low level software design Perform software testing including unit, functional and system level requirement including manual and automated Performs software requirement to design to coding to testing traceability Performs code review following coding guidelines and static code analysis Troubleshoots software problems of limited difficulty. Documenting technical deliverable like software specifications, design document, code commenting, test cases and test report, Release note etc. throughout the project life cycle. Follow defined process for software Development life cycle Develops software solutions from established programming languages or by learning new language required for specific project. Experience / Skills Required Strong knowledge for Linux device drivers, Linux Kernel Programming, Linux Kernel Internals, Yocto / Buildroot or any other build systems Experience working with development tools like oscilloscope, protocol analyser, emulator, signal generator, JTAG programmer, GIT, SVN, JIRA. Experience working with different embedded microprocessor based on Qualcomm, TI, NXP, NVIDIA, Intel or similar Experience of Board support package, Device driver and boot loader development/porting. Understanding of hardware schematic, datasheet of hardware component to derive firmware/software specific solution Strong sense of ownership, passionate, fast learner, analytical mind set, perfection seeker. Personal Attributes The ideal candidate should have strong Team-work characteristics, being both action and results- oriented. He/she will be a hands-on, roll-up-the-sleeves type engineer with a whatever it takes to get it done attitude. The successful candidate must be effective operating in a multi disciplined technology environment coupled with an obsession for responsiveness to Project requirements. The successful candidate should be open to learn new processes and technologies.

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Custom Compute & Storage - CCS BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast‐growing product lines, Marvell technology is powering the next‐generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect As a Senior Director, you’ll be responsible for collaborating with various teams to develop strategies, pushing the IP roadmap, and supporting multiple SOCs. This starts at the product definition phase with architecture and marketing then continues through execution of all efforts required including supporting productization. You’ll provide leadership in the development of highest value-add IP, subsystem & SoC plans and strategies with cutting edge process, speed and performance designs. The planning and execution need to be rationalized with budget and market timing requirements. Experience and judgement in determining the value of the tasks defined and executed by the team is important. This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology looking for ways to improve the value and quality of the effort while keeping cost in budget. Manage and continue to build a team of complex sub-system, co-processors, accelerator and SoC engineers. The managed team includes design, verification, and collaborating with the Physical Design, DFT & Validation teams. Develop methodologies and infrastructure with evolving technology challenges including cutting edge semiconductor process, I/O’s, networking bandwidth, embedded cores, and co-processors. Work with architecture, SoCs, software, firmware, program management and post-silicon design teams for plan development and execution. Provide technical mentoring for team members. Actively engage in efforts to find improvements in methodologies, techniques, and automation Own schedules and reporting of progress metrics What We're Looking For 25 years of relevant industry experience in Semiconductor design & development Demonstrated ability to lead a multi-disciplinary team, show initiative, collaborate and communicate effectively with team members across functions & cultures. Experience in all phases of design from concept through productization. Understand & appreciate the complexity of data centers, server class or networking chipsets & prior experience with successful first silicon success. Ability to recruit and retain engineering talent. Demonstrated mentoring of junior staff. BS degree or higher in EE or CE or CS with 25+ years or more of RTL and/or verification experience 10 + years of experience managing a Design/DV/Emulation & related teams. Preferred Qualifications Experience with Full chip design, development & emulation of complex designs targeting Datacenters, Servers, Enterprise/Networking domain. Expert in developing IP, subsystem, Chiplets and SOCs Experience with one or more high-speed IO technologies: DDR, PCIe, CXL, Ethernet Management of cross-site teams Knowledge of industry standard SOC components (bus fabrics, I/O devices, processors) Knowledge of HW-SW co-development and silicon validation cycle Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

JD for Construction Quality Executive Hyderabad Site:- 4 years as Construction Quality Engineer/ Executive Conduct the CCIP audit independently in any P&G site or other site . Experience of various concrete methods & technologies, Post tensioning, Conventional, Mivan methods, etc. Worked on Quality management Systems to fulfill the construction process, E-QOS, SOP, CBA requirements, CSA, PEB, HVAC, Fire protection system, Welder qualification WPS, PQR, WPQR, clean room standards, Post tensioning, Quality scope & LEAN IPD, Big Room & Last Planner System, BOQ. SOW, CCIP & CSPA audit, Continuous improvement of quality & site standards Experience of various concrete floors, conventional, Grade slab, Vacuum dewatering floor, Deck slab, etc. Experience of finish floor densification by Calcium & Lithium silicates as required co-efficient of friction of floor. Experience in various flooring work, (PU) Polyurethane flooring & Epoxy flooring, etc. Experience of architecture work, dry wall partitions, ceiling work (Fire rated & non fire rated), floor & wall tiling, wall putty, primer & paint work, QRS, etc. RMC/Batching plant ISO requirements. To check for calibration of instruments and checking material tested certificates from the agencies. Implemented the Mockups & trainings for new activities & as well as all engineers, supervisors & workers to avoiding standards & quality deviation. Communication Skill should be English, Hindi, Telugu Strong Soft skill knowledge about advance MS office, report , graph etc. Familiar with test procedure, Destructive & Non-destructive tests. DP, UT, RT, DFT and technical specification as per IS, ASTM & ASME standard. Worked on Construction CIVIL work, Architectural -PEB, HVAC , Fire protection work

Job Description: Construction Quality Executive Location: Hyderabad Site Position: Construction Quality Executive Experience Required: Minimum 4 years of experience as a Construction Quality Engineer/Executive. Experience working on a P&G site in the last 5 years is an advantage. Key Responsibilities: Independently conduct CCIP audits at P&G sites or other construction sites. Apply various concrete methods and technologies, including post-tensioning, conventional methods, Mivan methods, etc. Manage and implement Quality Management Systems to support construction processes, including E-QOS, SOP, CBA requirements, CSA, PEB, HVAC, fire protection systems , welder qualification (WPS, PQR, WPQR) , clean room standards, post-tensioning, quality scope & LEAN IPD, Big Room & Last Planner System, BOQ, SOW, CCIP & CSPA audit, and continuous improvement of quality & site standards. Oversee the construction of various concrete floors, such as conventional, grade slab, vacuum dewatering floor, deck slab, etc. Ensure the finish floor densification by calcium and lithium silicates to meet the required coefficient of friction. Manage various flooring works, including polyurethane (PU) flooring and epoxy flooring. Supervise architectural work, including dry wall partitions, ceiling work (fire-rated and non-fire-rated), floor and wall tiling, wall putty, primer & paint work, QRS, etc. Ensure RMC/batching plant ISO requirements are met by checking instrument calibration and verifying material test certificates from agencies. Implement mockups and training for new activities and ensure all engineers, supervisors, and workers adhere to standards and quality to avoid deviations. Skills and Qualifications: Strong communication skills in English, Hindi, and Telugu. Proficient in advanced MS Office, including report generation and graph creation. Familiarity with test procedures, both destructive and non-destructive tests (DP, UT, RT, DFT), and technical specifications as per IS, ASTM, and ASME standards. Experience in construction civil work and architectural tasks, including PEB, HVAC, and fire protection work. Additional Information: The role demands a keen eye for detail and a commitment to maintaining high-quality standards. The candidate should be proactive, with the ability to lead and train teams effectively. Knowledge of continuous improvement practices and the ability to implement these in daily tasks is essential. Thanks & Regards Your Manpower Manager DIVYA SHARMA Contact No-6262000413 Officer- TA | HR Ashkom.hr1@ashkom.com Divya.ashkom@gmail.com Ashkom Media India Private Limited Website: www.ashkom.com

Alternate Job Titles: ASIC Design Engineer Digital Design Engineer Senior ASIC Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. PVT Sensor IP development is a critical offering for process, voltage, temperature, and other monitoring IPs within SOC subsystem. Synopsys is a market leader for these IP developments which are integral parts of Silicon lifecycle monitoring. You Are: As a new, exciting, and challenging position, we are looking for a talented person that can show a great level of initiative and ability to work in a busy and fast-changing environment. This rewarding role is fundamental to the successful and smooth operation of the engineering teams. You will play a vital role in helping to strengthen and develop forecasting capabilities, based upon improved monitoring capacity and forward-looking project schedules. You will generate test benches and test cases, perform RTL and gate-level SDF-annotated simulations and debug, and may perform mixed-signal (digital + analog) simulations and debug. You will interact with our application engineers and provide guidance to customers. Additionally, you will participate in the generation of data books, application notes, and white papers. What You’ll Be Doing: Generate test benches and test cases. Perform RTL and gate-level SDF-annotated simulations and debug. May perform mixed-signal (digital + analog) simulations and debug. Interact with our application engineers and provide guidance to customers. Participate in the generation of data books, application notes, and white papers. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Understand tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views. Write RTL Code, with solid Verilog, PERL, and Python skills, and TCL is a good addition. Understand static timing analysis and synthesis, DFT/ATPG skills would be a plus. Knowledge of any high-speed communication protocol is not mandatory but an asset. Previous knowledge in customer support and/or silicon bring-up is a plus. The Impact You Will Have: Strengthen and develop forecasting capabilities based on improved monitoring capacity. Ensure high-quality and reliable silicon lifecycle monitoring solutions. Enhance quality assurance methodology by adding more quality checks/gatings. Support internal tools development and automation to improve productivity across ASIC design cycles. Work with design engineers on new tools/technology and new features evaluation and adoption. Contribute to the successful and smooth operation of the engineering teams. What You’ll Need: Bachelor’s or master’s degree in electrical engineering or a related field. 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Who You Are: Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on developing cutting-edge PVT Sensor IPs integral to Silicon lifecycle monitoring. This team collaborates closely with other engineering teams to ensure the highest quality and performance of our products. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One Scripting languages like Make flow, Perl ,shell, python - Any One ASIC RTL Engineer Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Good understanding of timing concepts Knowledge of one or more of the interface protocols PCIe DDR Ethernet I2C, UART, SPI Expertise in setting up and using tools like Spyglass Lint/CDC Synopsys DC Verdi/Xcellium Understanding of scripting languages like Make flow, Perl ,shell, python etc Understanding of processor architecture and/or ARM debug architecture is a plus Able to help and debug issues for multiple subsystems Able to create/review design documents for multiple subsystems Able to support physical design, verification, DFT and SW teams on design queries and reviews. Show more Show less