1121 Dft Jobs - Page 39

RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One Scripting languages like Make flow, Perl ,shell, python - Any One ASIC RTL Engineer Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Good understanding of timing concepts Knowledge of one or more of the interface protocols PCIe DDR Ethernet I2C, UART, SPI Expertise in setting up and using tools like Spyglass Lint/CDC Synopsys DC Verdi/Xcellium Understanding of scripting languages like Make flow, Perl ,shell, python etc Understanding of processor architecture and/or ARM debug architecture is a plus Able to help and debug issues for multiple subsystems Able to create/review design documents for multiple subsystems Able to support physical design, verification, DFT and SW teams on design queries and reviews. Show more Show less

COMPANY PROFILE eInfochips – An Arrow Company (www.einfochips.com) is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company’s service offerings include digital transformation and connected IoT solutions, Including IoT Security, across various cloud platforms, including AWS and Azure. Our work culture is built over years of experience in providing innovative solutions to our clients and our indomitable spirit to excel in all aspects of our engagement. We believe that our success lies upon the skills and quality of our people we work with. Silicon engineering services: ASIC / FPGA Design & Development, Design Verification & Validation, Physical Design & DFT Embedded systems engineering services: Hardware Design, System Software, System Verification & Validation, Multimedia Software engineering services: Cloud Enablement, IoT & Mobility, Application Software, QA and Test Automation, BI and Data Visualization Extended services: New Product Development, Lifecycle Management, Product Sustenance IPs: DevOps for IoT, IoT Gateway Framework, IoT Device Lifecycle Management, Video Management Software, Reusable Camera Framework, Test Automation Framework, Reference Designs & EVMs, Verification IPs, OptiX – Physical Design Framework Our Core Values Customer First Disciplined Execution Embrace Impossible Challenges Continous Learning Service Society Job Description Summary *Analyzing the requirement documents and discuss queries with client. *Key objectives for this role will include test scripts development, reviews, test execution & bug reporting. * Prepare automation design documents based on documented project requirements and team discussions. *Test Execution in all levels of testing including Functional Testing, Smoke Testing, Integration Testing, Regression Testing, Load Testing, System Testing etc. *To Perform testing of key web, cloud, device and mobile application projects. *Incumbent will have to Identify, prioritize and execute tasks in testing life cycle. * To Work with other leads on developing continuous integration (CI) pipeline and test automation framework and need to document the work. *Provides support to junior QA team members. Job Complexity *Incumbent works under general supervision *Incumbent has substantial experience to resolve problems and concepts *Incumbent can work on complex concepts and implementation Technical Skills Expertise in PyTest framework and embedded testing using Python. Understanding of PyTest automation frameworks and RESTful API testing. Hands on experience in performance testing for Embedded platforms. Should be open to work on any tools, technology, projects as per business needs. Good to have exposure on agile scrum, test management tool like Testlink, JIRA, QC, etc. Good to have experience with CI tool like Jenkins. 5+ Years experience in Automation Testing Work Location Ahmedabad/Pune/Hyderabad Einfochips is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, sexual orientation, gender identity, national origin, veteran or disability status Show more Show less

RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One Scripting languages like Make flow, Perl ,shell, python - Any One ASIC RTL Engineer Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Good understanding of timing concepts Knowledge of one or more of the interface protocols PCIe DDR Ethernet I2C, UART, SPI Expertise in setting up and using tools like Spyglass Lint/CDC Synopsys DC Verdi/Xcellium Understanding of scripting languages like Make flow, Perl ,shell, python etc Understanding of processor architecture and/or ARM debug architecture is a plus Able to help and debug issues for multiple subsystems Able to create/review design documents for multiple subsystems Able to support physical design, verification, DFT and SW teams on design queries and reviews. Show more Show less

Pune, Maharashtra, India Department Electronics Job posted on May 28, 2025 Employment type Permanent Generate Schematic, layout as per Designer guidelines and IPC standard Design single sided, double sided and multi-layered PCB’s using industry standard techniques, ensuring consideration for DFM/DFT have been made. Working with HW Engineers to develop Schematics. CAD library administration including symbol, footprint generation. Creation of 3D models and assemblies from 2D layouts BOM data management in the PLM (Part life cycle management tool) Work closely with CFT team to create robust designs Work with the manufacturing team for procurement and transfer of documentation Contributing to continual process improvement within the PCB layout function DFM review with EMS and Quality team and update the design accordingly

Role Description We are looking for a Hardware R&D Engineer who is passionate about developing innovative electronics for real-world applications. In this role, you'll be involved in the entire product development lifecycle from concept and prototyping to testing and final production. If you're experienced in PCB design, embedded systems, and electronic debugging, and enjoy working in a collaborative and fast-paced environment, we'd love to meet you! Key Responsibilities Design and develop Printed Circuit Boards (PCBs) using tools like Altium, Allegro, or PADS. Perform schematic capture, layout design, and BOM optimization. Conduct simulation, testing, and validation of analog/digital circuits and embedded systems. Interface hardware with firmware/software to ensure full system compatibility. Debug prototypes using lab equipment like oscilloscopes, logic analyzers, and multimeters. Ensure designs comply with industry standards and certifications (CE, FCC, RoHS). Prepare performance reports, test documentation, and support the manufacturing handover. Stay up to date with emerging technologies in IoT, embedded systems, and power electronics . Required Skills & Qualifications Bachelor's degree in Electronics & Communication (ECE) , Electrical, or related field. Minimum 3 years of hands-on experience in hardware design or embedded product development. Experience with microcontrollers and embedded platforms (ESP32, STM32, MSP430, etc.). Proficient with interface protocols like UART, SPI, I2C, CAN, and USB. Ability to read schematics, debug hardware, and analyze signal/data integrity. Familiarity with EMI/EMC practices , DFM/DFT, and design compliance requirements.

Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position will be responsible for Architecting, Leading and implementing DFT / Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs The execution involves Design-for-Test Architecture definition, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What Were Looking For Bachelors degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience. Hands on working experience in various stages of DFT-Execution SCAN-Insertion / MBIST / ATPG / Validation / STA / IP-DFX / Post-Silicon Bringup/Debug Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs. Strong fundamentals in Digital Circuit Design and Logic Design is required Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus, Modus, NCSim / DC, Tessent, Spyglass/Tmax) Prior experience in ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus

Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position is for a Techno-Managerial role who will be responsible for Managing a team of skilled DFT-engineers who work on implementing DFT / Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs. The management responsibilities include but not limited to handling career-development, mentoring and monitoring project execution. As a senior technical leader, the role also involves driving end to end DFT-execution on SoCs and Subsystems, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience. Management experience - Must have directly managed small sized teams , members HandsOn Working experience in various stages of DFT-Execution SCAN-Insertion / MBIST / ATPG / Validation / STA / IP-DFX / Post-Silicon Bringup/Debug Strong fundamentals in Digital Circuit Design and Logic Design is required Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus, Modus, NCSim / DC, Tessent, Spyglass/Tmax) Prior experience in Custom-ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Front-end implementation from RTL to netlist, including RTL Lint, CDC/RDC analysis, timing constraints, Power Analysis, STA for Multi-Media IPs Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. Analyze the inter-block timing and come up with IO budgets for the various partition blocks. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Perform RTL Lint and work with the Designers. Analyze RTL CDC/RDC and work with Designer for potential Clock and Reset Design Domain crossing issues. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities. Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). Implementing Functional ECOs using Conformal and writing manual Ecos. Work with Architects, RTL Designers and SOC teams for efficient IP Quality. PREFERRED EXPERIENCE: 5 to 10 years of experience in Front-end implementation from RTL to netlist Familiarity with Power Analysis Experience/Background on Computing/Graphics is a benefit ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

The Design Methodologies and Tools Engineer / Architect develops and applies Computer Aided Design (CAD) software engineering methods, theories and research techniques in the investigation and solution of technical problems. Assesses architecture and hardware limitations, plans technical projects in the design and development of CAD software. Defines and selects new approaches and implementation of CAD software engineering applications and design specifications and parameters. Develops routines and utility programs. Prepares design specifications, analysis and recommendations for presentation and approval. May specify materials, equipment and supplies required for completion of projects and may evaluate vendor capabilities to provide required products or services. KEY RESPONSIBILITIES: Provide technical leadership to define, enable, implement, automate and drive tool/flow/methodology to improve SoC integration efficiency. quality, cost and predictability. Work with architects and design team to understand and continuously improve design process from specification to tapeout. Interface with the architecture, SoC integration, power, Design implementation, Power, Design Verification and Physical design teams to identify complex technical issues/risks and optimize the implementation efficiency and cost. Support the SoC Design and Integration team on project execution. You should be familiar with SoC level Clock and Reset, low power design, UPF, CDC/RDC/LINT, DFT, top level integration of connectivity, system bus, peripherals and processor. We are looking for someone who is technically hands on and a great team player. PREFERRED EXPERIENCE: Bachelors or masters degree in related discipline with 15+ years experience preferred. Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: SoC integration, Frontend-design, Design Verification, Design Emulation, System/performance/power modeling, Design handoffs, Design management, Design reuse, CAD/Automation algorithms. Experience analyzing Design and Verification methodologies/flows to identify bottlenecks, left-shift opportunities, and Demonstrated tools / flows / methodologies / automation expertise in SoC integration, Verification, Emulation, low power design, power optimization, Functional Safety, System modeling, Synthesis and anlysis. Experience with scripting in Perl, Python, TCL, and C/C++. Excellent communication and problem solving skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies.

Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position will be responsible for implementing and validation DFT/Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs The execution involves Implementation of various DFT/DFX features, Scan/MBIST Insertion & Validation, ATPG , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 8+ years of experience. Hands on working experience in various stages of DFT-Execution SCAN Insertion / ATPG / MBIST / Validation / STA / IP-DFX / Post-Silicon Bringup/Debug Strong fundamentals in Digital Circuit Design and Logic Design is required Knowledge on various DFT/Test solutions Understanding of DFT Flows and Methodologies and Experience with Siemens/Synopsys/Cadence Tool set (Tessent/DC, Spyglass, Tmax, VCS/Genus, Modus, NCSim ) Prior experience in ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus

The Opportunity Were looking for the Wavemakers of tomorrow. Alphawave Semi is expanding its team in Chiplet Architecture and Design! We are looking for experienced RTL Design Engineers to contribute to our next generation Chiplet designs. This is an incredible opportunity to be part of the AI revolution and engage in the complete ASIC development cycle, from concept to product. We are seeking a seasoned SoC leads to work with a team to solve complex problems while optimizing performance, area, and power on leading-edge SoC systems. This team helps build new and innovative connectivity products tailored to world changing solutions for AI accelerators, Compute, IO, and Memory Chiplets. What Youll Do: You will manage the design / RTL team to achieve the project goals You will work with customer, provide technical support and provide collaterals agreed upon. You will work with team to achieve flow, methodology improvements to achieve high reuse. You will work with IP vendors to generate / get right configurations of the IP. You will manage teamwork allocation, schedule, risk mitigation and deliverables from design team. Interact closely with the architecture team and develop implementation strategies to meet quality, schedule, and power performance area for the SOC. Interact with the subsystem team and plan SOC milestones, plan quality checks as part of SOC milestones and guide subsystem teams with SOC level requirements (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.). Work with the cross-functional team of verification, DFT, Physical Design, emulation, and software teams to make design decisions and represent Design status throughout the development process. What youll have: Education: Bachelors or masters degree in electrical or Electronics and Communication or Computer Science Engineering. Experience: 15+ years of proven experience in SoC architecture, development, and full-chip design for multi-million gate SoCs. Expertise: Strong understanding of the design convergence cycle, including architecture, micro-architecture, verification, synthesis and timing closure. Expertise in managing IP dependencies, as well as planning and tracking front-end design tasks. Ability to drive project milestones across design, verification, and physical implementation phases. Experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains is highly desirable. Skills: Excellent communication and interpersonal skills. Ability to collaborate in a fast-paced, product-oriented, and distributed team environment. Minimum Qualifications: SoC Design Experience: Minimum 15+years of hands-on experience in SoC design. Architecture Development: Ability to develop architecture and micro-architecture based on specifications. Bus Protocols & Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc. Memory Controllers & Microprocessors: Experience with memory controller designs and microprocessors is an advantage. Chip IO Design: Knowledge of chip IO design and packaging is beneficial. Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics. Synthesis & Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC. Timing Closure: Comprehensive understanding of timing closure is mandatory. Post-Silicon Debug: Experience in post-silicon bring-up and debugging. Decision Making: Ability to make effective decisions under incomplete information. Communication & Leadership: Strong leadership and communication skills to ensure effective program execution. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Great compensation package Restricted Stock Units (RSUs) Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll do: Responsible for front end implementation of IPs which includes Synthesis, LEC, CLP. Collaborate with designers and PNR teams to achieve design closure with focus on Quality Ability to debug and resolve technical issues. Hands on functional ECO generation using Candence conformal LEC Should be able to provide good support to Gate level simulations (GLS) team Overall, should have good knowledge on RTL so as to understand all synthesis related warnings. What Youll Need: 5-7 years experience in physical aware synthesis. Self-motivated complete understanding of timing constraints, low power aspects and concepts of DFT Experienced in synthesis, LEC, CLP and timing closure Should have handled blocks with complex designs, multiple high frequency clocks and complex clocking. scripting and automation experience is a must. We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Pcb design engineer Mysore location Minimum of 10 years of experience in PCB design and schematic capture with expertise in Altium Designer. Strong understanding of Analog and Digital circuit design. Experience in high-speed PCB routing and signal integrity analysis. Knowledge of EMI/EMC guidelines for PCB design. Familiarity with IEC 60601-1 and IEC 60601-1-2 standards Experience with cable assembly drawings in Altium designer. Ability to interact with PCB/PCBA manufacturers and suppliers to resolve technical issues. Knowledge of DFM (Design for Manufacturability), DFT (Design for Testability), and DFA (Design for Assembly) principles. Knowledge of thermal management techniques in PCB design Strong analytical, troubleshooting, and problem-solving skills. Excellent communication and teamwork skills.

RoleFront-End RTL Design Automation Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a Senior CAD Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What You Need To Have Tech/B 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks Show more Show less

RoleSenior CAD Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a Senior CAD Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What You Need To Have Tech/B 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks Show more Show less

RoleASIC CAD Lead Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a ASIC CAD Lead Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What You Need To Have Tech/B 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks Show more Show less

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.Proven expertise in analysing and resolving DRCs/TSVs .Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .Hands on experience on industry standard tools used for DFT featuresProficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.Excellent analytical and problem-solving skills, with a keen attention to detail.Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design * Experience working with ATE engineers for silicon bring up, silicon debug and validation. * Experience in processor flow and post silicon validation Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075701 Show more Show less

We are looking for a Junior Hardware Engineer to join our dynamic team and contribute to cutting-edge technology solutions. This is a full-time on-site role for a Junior Hardware Engineer located in Goregaon east Mumbai. Responsibilities Design Development, testing & Debugging in the following field: high speed digital, analog, processor etc. Component selection and developing BOMs. Designing hardware circuits for Analog/ Digital/ Mixed Signal using microcontroller and 32bit processor experience in NPD projects. Support for developing embedded system products including writing requirements, standards, manuals, test procedures and test reports for such products Co-ordinate with production house for manufacturing Experience in DFMA , DFT and other NPI process Conduct hardware troubleshooting and debugging to ensure optimal performance. Prepare technical documentation and reports for hardware projects. Collaborate with other teams. Qualifications BE. / B. Tech in Electronics & telecommunication/ instrumentation or similar. 3-8 years in Electronics embedded hardware design , development and production Computer-aided design (CAD) skills on any design tool. (Altium preferred). Strong knowledge of various communication protocols like UART, I2C, SPI, USB, and their integration within the system. Experience in 16bit/ 32-bit ARM microcontroller-based electronics development. Hands-on skills with testing equipment such as Multi-meters, Scopes, DCAs, Logic Analyzers, and Spectrum Analyzers. Exceptional hands on skills in circuit assembly: Through hole and SMD Experience with DFMA, DFT and other production NPI process. Stay updated with industry trends and willingness to learn emerging technologies. Other Skills- Good communication skills Writing and documentation skills. Good research, team-work skills and interpersonal skills Willingness to work overtime if required. Ability to work independently and collaboratively Benefits- Salary is negotiable based on experience Annual increase Annual bonus Health policy for self and family 5 days working week (8 hours per day 10.00am to 6.00pm) 10 Public Holidays each year 12 Casual Leaves 12 Sick Leaves 15 Privilege Leaves Compassionate Leave To apply please use the link:- https://wrkbl.ink/4b4tck8 Show more Show less

Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization. What you will do: Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology. Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies. Good understanding of different CTS strategies and providing the feedback to Implementation Team. As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work. STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows. Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Good scripting skills (TCL/SHELL/PERL/Python) is a MUST Who you are: You are an ASIC engineer with 6+ years of related work experience with a broad mix of technologies including: All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation approach, Timing closure, physical convergence. Power Integrity Analysis Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies. Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies. You should also have hands on experience with the following Tool sets Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2 Synthesis Tools: Synopsys DC/FC Formal Verification : Synopsys Formality and Cadence LEC Static Timing verification: Primetime-DMSA Power Integrity : Apache Redhawk Physical Design Verification Synopsys ICV, Mentor Calibre Scripting: TCL, Perl is required; Python is a plus Bachelor's degree in Telecommunications Engineering, Computer Science, MIS, or related experienceWe are looking for high achievers who love challenging environment to join our team. We Are Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference. Here’s how we do it. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (30 years strong!) and only about hardware, but we’re also a software company. And a security company. An AI/Machine Learning company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box! But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.) Day to day, we focus on the give and take. We give our best, we give our egos a break, and we give of ourselves (because giving back is built into our DNA.) We take accountability, we take bold steps, and we take difference to heart. Because without diversity of thought and a commitment to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Show more Show less

Responsibilities DFT Engineer Bangalore, India 6+ years experience in DFT In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis Analyze design and propose best compression technique Debug and resolve the DRC issues Work with front end team to provide the solutions and make sure DFT DRCs are fixed Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is required In depth knowledge and hands on experience in MBIST insertion and Memory test validation Expertise in Mentor tools is plus Bachelors Degree in Electrical, Electronics or Computer Engineering Show more Show less

locationsIndia, Bangalore time typeFull time posted onPosted 9 Days Ago job requisition idJR0274850 Job Details: About The Role : We are looking for Senior DFT Design Engineers to join our team who are ready to make significant impacts in graphics and visual computing. As a member of the GHI DFT group, you will be responsible for one or more of the following activities: You will work on the design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG and/or DFT/JTAG controller You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types you are responsible for. Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration of the GPU block. Qualifications: The ideal candidate will exhibit the following traits/skills: Excellent written and verbal communication skills Demonstrate Leadership ability in driving execution Demonstrate teamwork, problem solving and influencing skills Ability to work with different geographical locations Minimum Qualifications: Bachelors in Electrical/Computer Engineering or related field with 9+ years of experience. Or a Masters in the same fields with 7+ Years of academic or industry experience. Your experience should be in following At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST) (This is a key skill requirement.) SoC or IP DFT design, integration or verification EDA tools such as ATPG tools, Siemens Tessent shell, VCS simulation and/or debug tools. Preferred Qualifications: Silicon enabling debug or test pattern development experience Design automation skills and proficiency in programming or scripting languages Structural design flows, including timing, routing, placement or clocking analysis High volume manufacturing requirements and test flows 3D, media and display graphics pipelines SoC architecture Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Looking for below - Architect/Lead ASIC designer/Lead Design verification/Lead Formal Verification/Lead Emulation/Lead Synthesis Engineer/Lead Implementation Engineer/Lead DFT Engineer/Lead Share your updated CV at jatin@smrd.in

As an RTL Design Engineer, you will work in SoC design and SOC-Subsystem design. You will be responsible for microarchitecture/RTL coding of the SOC/subsystems and create microarchitecture documents. You will work with verification teams on achieving the code functional coverage. You will work with Physical design team to meet area, power and performance goals. You will support physical design teams, verification teams, software teams and FPGA teams to ensure high quality SoC and ensure successful tapeout. What Youll Do: Micro architect and RTL Design of SoC SubSystem/IP blocks Will develop UPF and run CLP checks Will be responsible for RTL quality checks - Lint/CDC/LEC Create appropriate documentation for hardware blocks. Responsible for analyse / debug / fixing issues reported by verification team Will develop the synthesis constraints for the blocks / subsystem Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation What Youll Need: Education: Bachelors or masters degree in electrical or Electronics and Communication or Computer Science Engineering. Experience: 5+ years of proven experience in SoC architecture, development, and full-chip design for multi-million gate SoCs. Expertise: Strong understanding of the design convergence cycle, including architecture, micro-architecture, verification, synthesis and timing closure. Expertise in managing IP dependencies, as well as planning and tracking front-end design tasks. Ability to drive project milestones across design, verification, and physical implementation phases. Experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains is highly desirable. Skills: Excellent communication and interpersonal skills. Ability to collaborate in a fast-paced, product-oriented, and distributed team environment. Minimum Qualifications: SoC Design Experience: Minimum 5+ years of hands-on experience in SoC design. Architecture Development: Ability to develop architecture and micro-architecture based on specifications. Bus Protocols Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc. Memory Controllers Microprocessors: Experience with memory controller designs and microprocessors is an advantage. Chip IO Design: Knowledge of chip IO design and packaging is beneficial. Test Plans Verification: Proficient in reviewing high-level test plans and coverage metrics. Synthesis Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC. Timing Closure: Comprehensive understanding of timing closure is mandatory. Post-Silicon Debug: Experience in post-silicon bring-up and debugging. Decision Making: Ability to make effective decisions under incomplete information. Communication Leadership: Strong leadership and communication skills to ensure effective program execution.