1121 Dft Jobs - Page 44

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems for their immediate team and across multiple teams Lead the application design and development process Coordinate with stakeholders to gather requirements Ensure project milestones are met Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG) Strong understanding of software development lifecycle Experience in application architecture design Knowledge of database management systems Hands-on experience in application testing Additional Information: The candidate should have a minimum of 7.5 years of experience in Automatic Test Pattern Generation (ATPG) This position is based at our Bengaluru office A 15 years full-time education is required Qualifications 15 years full time education

ATE Senior Test Engineer Job Description In your new role you will: Develop and document Test plan for new MCU devices. Design and debug ATE Test Hardware and Software Production & Reliability. Debug new silicon on Automated Test Equipment. Bring quality and cost-effective Test solution for mass production. Oversee test related activities (HW & SW) with both internal and external Test house. Implement Test programs, modify and release into offsite production. Your Profile You are best equipped for this task if you have: Good understanding of semiconductor device fundamentals (Analog/Digital and Circuit Theory) Sound understanding of Semiconductor Design for Test (DFT) techniques such as ATPG and PMU blocks like BUCLK and LDO s with Trimming procedure. Expertise in Semiconductor Testing Methodology, using Advantest-93k. Good programming skills in writing and debugging test programs and HW related issues. Competency in programming with Scripting languages (ie., Perl/Python) and high-level languages (ie., C/C++, JAVA, Visual Basic) Develop and debug characterization and production test programs for microcontroller products on digital/Mixed signal/PMU blocks. Good verbal and written communication skills are expected. Familiar with UNIX/LINUX environment, commands and shell scripts. Contact: Jyoti.Vimal@Infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone.

We are seeking a proactive and detail-oriented Program Manager to oversee the planning, execution, and delivery of multiple product development and manufacturing programs. This role requires strong leadership, cross-functional coordination, and a deep understanding of electronics manufacturing process and product life cycles. Requirements Bachelor s degree in Electronics Engineering or related technical field. 5 7 years of experience in NPD program or project management within the electronics or manufacturing industry. Strong understanding of product development processes (concept to launch), manufacturing methods, and supply chain dynamics. Understanding of QMS requirements for different product verticals eg: Medical, Automotive, Industrial etc.. Hands-on experience in managing multiple new product introductions within the time line with 100% FPY Solid understanding of DFM, DFT, and BOM structuring. Strong problem-solving, analytical, and organizational skills. Excellent communication and interpersonal abilities to manage stakeholders at all levels. Responsibilities NPD Leadership: Manage and lead new product development programs from concept through to production ramp-up, ensuring alignment with business objectives. Program Planning: Develop and maintain comprehensive NPD program plans, including scope definition, timelines, resource planning, deliverables, and milestones. Cross-functional Collaboration: Work closely with engineering, product management, supply chain, procurement, manufacturing, and quality teams to ensure integrated execution. Technical Coordination: Drive coordination between design, prototyping, validation, and manufacturing readiness activities for new products. Risk & Issue Management: Identify potential risks to program success and implement mitigation plans. Act as the central escalation point for issue resolution. Customer & Stakeholder Engagement: Interface with internal and external stakeholders to define product requirements, provide regular program updates, and manage expectations. Change Control: Manage change requests related to design, specifications, schedules, or resources and ensure proper documentation and communication. Cost Management: Track and control program costs, work with teams to optimize cost performance, and support BOM cost evaluation. Regulatory & Quality Compliance: Ensure new products comply with quality standards and relevant regulatory requirements (e.g., UL, CE, RoHS, EMC). Supplier/Vendor Coordination: Collaborate with suppliers and contract manufacturers to ensure timely availability of prototypes and production components. Program Reporting: Provide regular status reports, dashboards, and risk updates to senior management and project stakeholders. Process Improvement: Identify and implement opportunities for continuous improvement in NPD processes and tools.

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. We are seeking a skilled and hands-on DFT Engineer (Level 5) to contribute to the Design-for-Test (DFT) implementation for SoCs. This role requires strong technical expertise in scan, MBIST, boundary scan, STA closure, and silicon readiness to support high-volume SoC products. You will work in a cross-functional team environment alongside RTL, physical design, and test engineering teams. Why This Role As an L5 DFT Engineer, you will play a critical hands-on role in defining and implementing Design-for-Test (DFT) strategies for next-generation SoCs. This role offers you the opportunity to work at the heart of silicon development, collaborating with architects, RTL designers, physical design, and test engineering teams to ensure silicon is testable, and production-ready. If youre a self-motivated engineer who thrives in technically challenging environments and is passionate about high-quality, high-coverage test solutions, this role is an ideal platform to balance of technical depth, collaboration, and impactful execution on real silicon products. Key job responsibilities Insert, and verify DFT logic and components in subsystem RTL netlists. Enhance and improve DFT implementation to achieve DFT coverage targets. Review sign-off level, timing closure using static timing analysis of DFT mode. Generate and sign off high-quality pre-silicon DFT patterns. Education: BS/BE or MS/ME in Electrical/electronic or Computer Engineering or related discipline. Experience: Minimum 5+ years in semiconductor industry as a DFT engineer Technical Expertise: Insert, and verify DFT logic and components in subsystem RTL netlists. Enhance and improve DFT implementation to achieve DFT coverage targets. Generate and sign off high-quality pre-silicon DFT patterns. Scan / ATPG: Hands-on experience in scan insertion and ATPG pattern generation for high fault coverage. Debugging RTL/Gate-level mismatches during scan simulation. Experience with IEEE 1500, 1687 (IJTAG) for core-level DFT integration. MBIST / Memory Repair: MBIST, BISR, and BIHR insertion tools and methodologies. Familiarity with shared-bus MBIST architecture is a plus. Experience in memory repair signature generation and validation. Boundary Scan & IJTAG: Working knowledge of IEEE 1149.x (Boundary Scan), and 1500, and 1687 IJTAG implementation. IJTAG ICL extraction, PDL modeling using Siemens Tessent (is a plus) or equivalent. STA / Timing Closure: Static timing analysis (STA) with DFT constraints for shift and capture paths. DFT-aware timing closure in collaboration with physical design teams. Automation & Scripting: Experience in developing automated workflows using Python, Tcl, or Perl. Reusable scripts for DFT flow integration, reporting, and analysis. Soft Skills & Collaboration: Strong communication skills; ability to collaborate with RTL, physical design, test, and PE teams. Debug / Post-Silicon: Post-silicon DFT pattern validation and silicon debug. Collaboration with ATE and Product Engineering teams for bring-up and correlation. Familiarity with failure triage using scan diagnosis tools. Soft Skills: Ability to work in a fast-paced, evolving environment Self-driven, detail-oriented, execution-focused. Team player with the ability to work across international teams.

We are seeking a highly motivated NPD Engineer to join our team. The ideal candidate will be responsible for Bill of Materials (BOM) scrubbing, Bom Review Analysis, and ensuring the feasibility of electronic PCBA and Box build assemblies. This role requires expertise in component selection, cost analysis, supply chain coordination, EOL management and working closely with cross-functional teams to ensure seamless product development. Requirements BE in Electronics/Electrical Engineering. 5+ years NPD & EMS experience in PCBA and Box build assemblies. Strong knowledge of analog/digital circuits, PCB layout, and embedded systems. Experience with prototyping, testing, and debugging. Understanding of EMS processes and QMS requirements. Excellent problem-solving and communication skills. Responsibilities BOM Management: Analyze, scrub, and maintain Bills of Materials (BOMs) for accuracy, completeness, and manufacturability. Design for Manufacturability & Testability (DFM/DFT): Conduct feasibility studies, risk assessments, and cost analyses to ensure optimized product design. Manufacturing Optimization: Optimize product designs for manufacturability.Develop process control parameters and ensure DFM compliance during development. Quality Assurance: Develop and implement test plans.Conduct process audits and manage supplier evaluations to ensure quality standards. Component Management: Monitor End-of-Life (EOL) components, suggest suitable alternatives, and manage engineering change control. Prototyping & Testing: Oversee the prototyping, testing, and validation of PCBA and Box Build assemblies. Process Development: Design and document manufacturing processes, ensuring adherence to quality, efficiency, and safety standards. Component Selection: Evaluate and select components based on cost-effectiveness, availability, performance, and longevity. Technical Documentation: Create and maintain detailed documentation, including SOPs, work instructions, checklists, assembly drawings, and test procedures. Problem Solving: Identify and resolve technical issues during product development and production phases. Cross-functional Collaboration: Coordinate with internal teams and external stakeholders to ensure alignment on product requirements and deliverables. EOL Management: Proactively manage component obsolescence and implement timely alternative solutions. Customer Interaction: Interface directly with customers to gather requirements, provide updates, and offer technical support

Develop and implement high-performance, low-power, area-efficientdigital designs for ASICs and SoCs using industry-standard EDA tools. Work closely with design teams to understand the requirements andconstraints of the design, and provide feedback on design feasibility,timing and power. Write and implement block level and top-levelconstraints for synthesis, perform timing closure and power analysis.Debug and resolve design issues related to synthesis, timing, power, andarea. Understanding of DFT flows, including scan insertion and ATPG.Optimize designs for power, performance, and area, and meet design goalswithin the given schedule. Implement pipelining at different levels forperformance optimization and timing closure. Perform power analysis andoptimize designs for low power. Proficient with EDA tools fromSynopsys/Cadence/Mentor. Excellent analytical & communication skills.Shown ability to collaborate in a multi-functional environment,cross-site or cross-time zone. Proficient in Tcl and Perl or otherscripting relevant language is a plus Your Profile Bachelors or Masters in Electrical/Electronics Engineering with 5+ yearsof relevant experience. In-depth knowledge of synthesis methodologies and tools from leading EDAvendors. Experience with writing design constraints for synthesis, timing closureand pipelining at different levels for performance optimization andtiming closure. Experience with power analysis and optimization flows such as powergating, clock gating, voltage scaling, and dynamic voltage frequencyscaling. Experience with scripting languages such as Perl, Python, or Tcl . Excellent problem-solving skills and ability to work independently andin a team environment. Strong communication and interpersonal skills, with the ability to interact effectively with cross-functional teams. Proven track record of delivering successful designs on time and meeting performance, power, and area goals.

Skills : Calibre,ICC2,Perl,TCL Total vacancies : 3 Experience on EMIR analysis for multiple modes, including; static and dynamic with/without functional vectors Should have expertise in understanding and debugging EMIR issues in a block level. Power analysis for the blocks. Experience on Floor-planning, Place & route, power and clock distribution, pin placement. In-depth knowledge on industry leading tools like Redhawk, Olympus/ICC2, Primetime, and Calibre Knowledge of package modeling, package and chip level analysis is added advantage Good understanding of Physical design verification using Calibre. Knowledge of Synthesis and DFT is added advantage. Prior experience with 16nm or finer geometries is a plus. Proficient use of tcl/Perl Must have good communication skills and self-driven individual

ADI is seeking a skilled Digital Design (Synthesis/STA) Engineer to support ASIC product development worldwide. This role involves close collaboration with Design-for-Test (DFT) engineers and Physical Design engineers to deliver comprehensive design implementation solutions for our business units. This position is part of ADI s Engineering Enablement group, with a strong focus on digital design implementation services. The ideal candidate is goal-oriented, self-driven, and upholds high professional standards while thriving in a team-oriented environment. Key Responsibilities Execute RTL Qualification, Logic Synthesis, Static Timing Analysis, and Equivalence Checking Develop and verify constraints, perform Timing/SI Closure, Power Analysis/Optimization, and implement low-power designs Collaborate closely with Design, DFT, and Physical Design engineers to provide front-end implementation services and support EDA tools and flows Maintain a deep understanding of automation flows and EDA tool functionalities Develop and refine Perl, Tcl, Ruby, and Shell scripts for process automation Minimum Qualifications MSEE with 1+ years or BSEE with 3+ years of industry experience in synthesis, STA, and equivalence checking Expert proficiency in DesignCompiler/Genus, PrimeTime/Tempus, and Conformal Experience in low-power/UPF implementation and Spyglass RTL checkers (preferred) Knowledge in timing/SI closure, DFT, and design verification (preferred) Familiarity with Verilog Strong programming/scripting skills in Perl, Tcl, Ruby, Shell, Java, Scala, and Python Excellent problem-solving, written, and verbal communication skills

Required Skills: The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills."

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelor's degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience. Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs Core DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax) Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl Proficient in Unix/Linux environments Strong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT) Strong understanding of software development methodologies Experience in leading and managing software development projects Knowledge of technologies and tools used in software development Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT) This position is based at our Chennai office A 15 years full time education is required Qualification 15 years full time education

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NA Minimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelor's degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience. Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs Core DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax) Experience coding in Verilog RTL, and scripting language like TCL, and/or Perl Proficient in Unix/Linux environments Strong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT) Strong understanding of software development methodologies Experience in leading and managing software development projects Knowledge of technologies and tools used in software development Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT) This position is based at our Chennai office A 15 years full time education is required Qualification 15 years full time education

"> Search Jobs Find Jobs For Where Search Jobs ASIC Digital Design Engineer, Senior Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 8686 Remote Eligible No Date Posted 28/01/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You possess a strong theoretical and practical background in high-speed serializer and data recovery circuits. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team. What You ll Be Doing: Developing and verifying digital designs for next-generation NRZ and PAM-based SerDes products. Running lint/cdc/rdc checks and synthesis flow. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Collaborating with mixed-signal engineers to deliver high-end mixed-signal designs from specification development to functional and performance tests. Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You ll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience with Verilog and VCS. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively. The Team You ll Be A Part Of: Join our highly experienced mixed-signal design and verification team, where you will work alongside experts in digital and mixed-signal engineering. Our team is dedicated to developing innovative solutions for the next generation of high-speed SerDes products, providing continuous training and opportunities for growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

We are seeking a Senior CAD Engineer with 10+ years of experience to join our team in Bangalore. The ideal candidate will be responsible for deploying and supporting front-end tools such as RTL simulators, low power tools, and static RTL checkers. They will also develop scripts to automate regression/debug flows, manage CI/CD processes, interface with EDA vendors, and support global teams across geographies. Proficiency in scripting (Python, Bash, Makefiles), Linux system administration, and version control tools (Git, Mercurial) is essential. Experience in ASIC flows and standard CAD tools is required. Immediate joiners with a notice period of 15 days or less are preferred.

Analyse customer requirements, legal regulations and internal specification to be applied in Testing strategies of productsDevelop EOLT specifications for new equipments (Hardware & Software)Design and develop complex test programs, process and systems to measure product functionality and integrality in the electrical and programming domainsAnalyse test cases and failure, providing scenarios and proposing actions based on resultsChecks product SW and Test Methodology/Coverage during DFT Design Review, with R&D interactionMay make himself some functional Tester software development and improvementsChecks the Functional Testers development (review of technical issues and planning)Work with the Software Validation Team to ensure complete test coverage of all requirementsAnalyze the customer specifications, legal requirements and internal specifications towards the development of electronic test plansSupport the creation of test equipment specifications and tester hardware specifications used in the development of automated test rack systems Perform validation, capabilities, test coverage and stability performance of testersMonitor testing TLR, analyse defects, and propose action plans to reduceValidate PG RAISE and CdC standards which are created by M/D Standard OwnersValidate any change of standard propose by sites in new investments for Testing equipmentsValidate the assembly line included on each CAA, in concept, cycle time and investment valuesContribute to product & process FMEA, assisting Testing technicians in daily activitiesSupport transition of newly developed processes into series production, providing process / equipment specification and qualificationDefine activities to permit integration of Testing equipments into more complex manufacturing cellsPerform survey of equipment in continuous improvement & cost reduction mindset to optimize investments, material & labor costsDevelop an industrial cross-project competencePromote the Valeo Industrial standard rules and proceduresEnsure the respect of Safety and Environment procedures of Valeo Group PS: if the workload justifies it, the function can be divided in more than one person

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Role Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.Experience in all aspects of timing closure for multi-clock domain designs.Should be familiar with MCMM synthesis and optimization.Should have good understanding of low-power design implementation using UPF.Experience with scripting language such as Perl/ Python, TCL.Experience with different power optimization flows or technique such as clock gating.Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validationShould be able to handle ECOs and formal verification and maintain high quality matrix Skill Set Proficiency in Python/Tcl Familiar with Synthesis tools (Fusion Compiler/Genus), Fair knowledge in LEC, LP signoff tools Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus Should be sincere, dedicated and willing to take up new challenges Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075441

Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. ASIC Frontend Implementation, CDC/RDC Responsibilities: Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC. Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC. Perform RTL Lint and work with the Designers to create waivers. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,). Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 8+ years of experience in static verification tools Experience with Lint, Clock Domain & Reset Domain crossing. Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 5+ years of experience in static verification tools Experience with communicating across functional internal teams and vendors. Experience with Lint, Clock Domain & Reset Domain crossing Experience with SOC CDC signoff Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL. Experience with communicating across functional internal teams and vendors. Preferred Qualifications: Experience with SOC Design Integration and Front-End Implementation Knowledge of Timing/physical libraries, SRAM Memories. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools. Experience with Netlist-CDC Analysis and improving MTBF Experience with developing structural rule based checks for RTL & Netlist Scripting and programming experience using Perl/Python, TCL, and Make Experience with SOC Design Integration and Front-End Implementation. Knowledge of Timing/physical libraries, SRAM Memories. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools. Experience with Netlist-CDC Analysis and improving MTBF Experience with developing structural rule based checks for RTL & Netlist Scripting and programming experience using Perl/Python, TCL, and Make. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

We are seeking a Senior CAD Engineer with 10+ years of experience to join our team in Bangalore. The ideal candidate will be responsible for deploying and supporting front-end tools such as RTL simulators, low power tools, and static RTL checkers. They will also develop scripts to automate regression/debug flows, manage CI/CD processes, interface with EDA vendors, and support global teams across geographies. Proficiency in scripting (Python, Bash, Make, Linux system administration, and version control tools (Git, Mercurial) is essential. Experience in ASIC flows and standard CAD tools is required. Immediate joiners with a notice period of 15 days or less are preferred.

PCB Design Engineer About Morphedo:Morphedo is a deep-tech innovation partner focused on accelerating product development in Aerospace & Defence, Medical Devices, and Smart Embedded Systems. We bring together expertise in electronics, firmware, mechanical systems, and industrial design to build complex, future-ready technologies. Role Overview:We are looking for a proficient PCB Design Engineer who will work as a key member of our Embedded Systems and IoT development team. This role demands close collaboration with hardware and firmware engineers to design PCB that are optimized for real-world embedded applications—considering system-level constraints such as power, EMI/EMC, and form factor. Key Responsibilities: Design and layout multi-layer PCBs from schematics for embedded and IoT devices using Altium Designer Integrate PCB layout with embedded firmware and mechanical housing constraints Work alongside firmware developers to align hardware design with software interfaces and performancerequirements Implement and validate design-for-EMC, signal/power integrity, and thermal considerations Generate and manage design deliverables including Gerber files, BOMs, pick-and-place data, and assemblyinstructions Perform DRC/ERC checks and lead resolution of issues across design iterations Maintain version-controlled libraries of footprints, symbols, and templates Support the prototyping, testing, and debugging of embedded hardware Contribute to continuous improvement of design workflows and documentation practices. Required Qualifications: B.E./B.Tech in Electronics, Electrical, or related field 2+ years of experience in PCB design with Altium Designer (mandatory) Solid understanding of embedded hardware design including microcontrollers, power regulation, sensors, andcommunication interfaces (I2C, SPI, UART, etc.) Experience with DFM, DFT, and low-power design strategies Strong understanding of PCB fabrication and assembly processes Ability to interpret firmware/hardware interactions to inform PCB design Preferred Qualifications: Familiarity with IoT protocols (BLE, Wi-Fi, LoRa, etc.) and RF layout techniques Understanding of EMI/EMC compliance and debugging Experience with hardware debugging tools: oscilloscopes, logic analysers, etc. Exposure to version control tools (e.g., Git) for collaborative hardware development Experience working in Agile or cross-functional development teams

Hiring Freshers Kickstart Your Career in VLSI At PRSsemicon Technologies, we are shaping the future of semiconductor innovation by building a Global Capability Development Centre. We are looking for fresh graduates passionate about VLSI domains to join our team. Through structured training and hands-on experience, we ensure you gain the technical expertise and industry-relevant skills required to succeed in this dynamic field. Your Journey with Us: Comprehensive Training Gain in-depth knowledge of VLSI design, verification, emulation, DFT, physical design, and analog design based on project needs. Hands-on Experience Work with industry-standard tools and methodologies. Expert Guidance Learn from seasoned professionals and build practical expertise. Live Project Transition Successfully complete training and contribute to real-world chip design projects. What We Look For: Strong fundamentals in Digital Electronics. Eagerness to learn and build competency before taking on project responsibilities. Passion for VLSI design and a commitment to a long-term career in semiconductors. Why Join PRSsemicon? Be part of Indias thriving semiconductor industry. Learn from experienced professionals in a structured training environment. Get hands-on exposure to cutting-edge chip design projects. Headquarter: Chennai Mode: Offline/Online/Hybrid (as per project requirements) Eligibility: B. Tech/M. Tech in ECE, EEE, E & I, VLSI, or related fields Year of passing out: From 2022 and below (2021, 2020.. ) will be considered Apply Now & Shape the Future of VLSI with Us!

Roles and Responsibilities Lead team of engineers for converting Customer concepts into efficiently designed products Select components, design and analyse circuits Design schematics and PCB layout designs using Altium, Allegro,, OrCAD tools. Conduct DFx analysis and value engineering improvement Generate Gerber and follow through for prototyping, validation and productionization Create system electrical interconnects for SPMs Conduct EMI/EMC testing and reverse engineering to identify design issues. Collaborate with cross-functional teams for obsolescence managements and retrofitting existing products. Report to group managers and program managers to ensure smooth execution and tracking of projects

Position Title: PCB Designer – Altium – Full Time Electrify Services is one of the fastest growing engineering services start up and is looking for a PCB Designer to play a key role of helping our client improve their product and take their business to the next level. This is an individual contributor role with a direct impact on company growth and customer satisfaction. We would like to see this position grow as company evolves. If you are looking for a high impact and challenging role, this job is a perfect destination for you! Major Job Duties We are looking for a PCB Layout Designer to optimize the design of PCBs with respect to layout, electrical and mechanical constraints, manufacturability, and relative costs of various alternatives.Ø Responsible with reading schematics, placing for low parasitic capacitance, inductance, and PCB layout techniques for power electronics circuits.Ø Review and analyze electrical design schematics and supporting documents to plan layout of PCB components and printed circuitryØ Perform and understand schematics capture, create, and troubleshoot net list and routing rules from customer provided information packages about the designØ Confer with engineers to resolve design details and problemsØ Perform placement and routing of PCBs for engineering review using AltiumØ Prepare PCB routing layout for engineering reviewØ Prepare PCB manufacturing data for use in PCB fabricationØ Generate accurate fabrication drawings, assembly drawings, and manufacturing artwork using Valor and Blueprint PCBØ Drive evolution of corporate PCB design standards by keeping current on underlying PCB materials technology, fabrication and assembly processes and their application in new products.Ø Conduct design feasibility studies to identify layout-related trade-offs on packaging, cost, manufacturing, and system performance for the engineering design team.Ø Own the responsibility of final design packages which include output file checks and the generation of fabrication and assembly documentationØ Build and maintain part libraries following the defined processes, ensuring they are complete and correct.Ø Collaborate with other team members as required Ø Other duties as assigned Required Qualifications:These responsibilities are just the start! At Electrify, we encourage you to contribute wherever your interests take you and shape your role accordingly. And this isn't just a philosophical bent: we give you 4 hours a week (10% of the work week) to pursue passion projects outside of your role responsibilities.We are Looking For People Who HaveØ EXPERIANCE WITH ALTIUM IS A MUST. MIN. 2 YEARS OF EXPERIANCES REQUIRED.Ø Proven PCB designer with experience in high voltage analog design, low voltage sensor signals and high-speed digital design.Ø Familiar with impedance-controlled circuits, layer stack-up trade-offs and panel optimization.Ø Ability to implement PCB design constraints driven from lists or schematics.Ø Must have actual DFM/DFT experience including the ability to make compromises between manufacturability, test, and electrical requirements.Ø Up-to-date knowledge of IPC standards and their application.Ø Ability to identify and resolve mechanical issues as related to PCB design.Ø Experience creating library components and managing libraries including 3D models of parts and PCBs to support accurate mechanical integration.Ø Must have a solid understanding of basic electronic circuitry and basic electromagnetics.Ø Ability to understand and apply best practices to minimize EMI/RFI and ESD issues.Ø Proficient using Altium Designer PCB software preferred.Ø Excellent communication skills, both verbal and written.Ø Ability to work one on one and in larger groups.Ø Familiar with Microsoft Office software.Ø Good communication skills.Location: Ahmedabad, India Salary: Depending on Experience and Past achievements. Send your Resume @ hr@electrifyservices.com

Job Category: Engineer Job Type: Full Time Job Location: Bangalore Join Mettlesemi s DFT design team to develop next-gen chips with a revolutionary architecture. Contribute to a multifaceted DFT approach, including architecture definition, logic design, verification, test pattern generation, and chip bring-up. Work in a dynamic, open, and fast-paced environment on cutting-edge silicon chip technologies. Shape the future of chips for top-notch clients. KEY JOB RESPONSIBILITIES: Senior DFT Engineer pivotal in device lifecycle, from definition to mass production. Collaborate with VLSI groups (chip design, verification, backend, test, and reliability). Develop, implement, and verify DFT on complex SOCS. Work closely with architecture team for DFT understanding. Ensure DFT design rules compliance with design teams. Collaborate with physical design team to meet DFT requirements. Expertise in SOC-level DFT techniques (ATPG, MBIST, JTAG, boundary scan). BASIC QUALIFICATIONS 6+ years chip design experience. 4+ years as a DFT engineer in a semiconductor company. Bachelor s/Master s in Electrical/Electronics Engineering. Strong post-silicon DFT bring-up and debug experience. Hands-on experience with multi-vendor DFT tools. Proficiency in ATPG tools (Mentor TK). Exposure to static timing analysis; timing closure. Excellent scripting skills in Perl/Tcl/Tk/Python. Knowledge of DFT technologies (JTAG, MBIST, Scan). Experience with RTL Coding (Verilog, System Verilog, VHDL). PREFERRED QUALIFICATIONS: Expertise in DFT methodologies (scan insertion, scan compression, boundary scan, memory BIST). Experience with DFT tools (Tessent, ATPG, MBIST, JTAG). Proficiency in Shell/Perl/Tcl and other scripting languages. Familiarity with ATE. Chip design, Verilog, and System Verilog. Verification, UVM methodology. ATPG tools, scan insertion tools, gate-level simulations. Static timing analysis. Scripting (Perl/Tcl). INTERPERSONAL SKILLS: Energetic, self-motivated Leader and Team player Proactive, detail-oriented, and quality-focused. Strong communication and reporting skills. Ability to collaborate with cross-national partners

Job Category: Design Job Type: Full Time Job Location: Bangalore About Us: Mettlesemi Systems and Technologies Pvt Ltd, based in Bengaluru, specializes in providing embedded systems, silicon solutions and related services. We have strong partnerships with top oplayers in the Semiconductor and Embedded Systems domain, across product development and prototyping. The Role: Mettlesemi is looking for exceptional engineers and engineering leaders to join our SOC development team to develop cutting-edge products within disruptive system architecture. You will have the oppertunity to work on the latest technologies in silicon chip design within a dynamic, open, and fast-peaced environment and develop the next generation of chips based on revolutionary architecture for our top-notch clients. Key Responsiblities: We are looking for talented Senior engineers to join our top-tier teams and participate in design and verification activities working on next-generation products, starting from the identification and definition of project requirements, architecture, and feature development. As a Design Engineer and integral part of the project team, your responsibilities will encompass the development of intricate Microarchitecture, Logic Design, Synthesis, Timing Closure, and Formal Verification using Formality. Collaboration with the Design Verification Team, the DFT Team, the Physical Design Team and other stakeholder teams will be a key aspect of your role. This presents a unique opportunity for you to make a significant impact across the entire product lifecycle. In this role, you will work in a team developing SoCs to be deployed in a range of products/applications. You will integrate industry-standard and custom hardware IP and subsystems into SoCs and will work closely with System Architects, SoC architects, IP developers, and physical design teams to develop SoCs that meet the power, performance, and area goals for these products/applications. BASIC QUALIFICATIONS 6+ years of experience in chip design. 5+ years or more of practical semiconductor design experience. Proficiency in Verilog/System Verilog. Fluent in scripting languages (TCL, Python). BE degree in Computer Engineering/BS Computer Science/Electrical Engineering. Excellent verbal and written communication skills. Strong collaboration and teamwork skills, ability to contribute to diverse and inclusive teams. PREFERRED SKILLS/EXPERIENCE Experience with the full SOC cycle Synthesis/STA/CDC/Lint. Experience with successful tape-outs of complex, high- volume SoCs in advanced design nodes. Experience with Design Automation. Experience in Designing protocols such as AMBA, LPDDR, DDR4 Strong working knowledge of Network on Chip (NOC), Coherent, and non-Coherent fabrics.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years"™ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Principal Duties and Responsibilities: 12+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts