1121 Dft Jobs - Page 43

Physical Design Engineer - Senior / Lead Job Description: Strong background in digital IC design , including floorplanning, placement, routing, clock tree synthesis, and optimization. Tools Expertise : Proficient in Innovus , ICC2 , and Fusion Compiler for place and route, timing closure, and physical design sign-off. Physical Design : Experience in floorplanning, placement, routing, clock tree synthesis (CTS), and static timing analysis (STA). Optimization : Focus on power , performance , and area (PPA) optimization. Sign-off : Conduct DRC , LVS , and parasitic extraction for clean designs. Advanced Process Nodes : Experience with 7nm , 5nm , or lower process nodes. Cross-functional Collaboration : Work closely with design, verification, and manufacturing teams. Tape-out : Drive tape-out process and ensure high-quality designs. Qualifications : Bachelor’s or Master’s degree in Electrical Engineering, with 4+ years of experience. Preferred : Experience with DFM , DFT , and advanced packaging technologies. Additional Skills : Proficiency in scripting languages like TCL , Perl , or Python for automating design tasks. Excellent problem-solving skills and attention to detail. Strong communication skills and the ability to collaborate effectively in a team environment. Experience: 4 to 8 years Location: Bangalore / Hyderabad Job Title : Physical Design Engineers Mandatory skills : Fusion compiler and PNR Notice Period : 0-30 days Show more Show less

KEY EXPERTISE Seasoned ASIC Front End leader with 20 years of cross domain experience ranging from architecture, uArch, IP/Sub- systems/SOC/ chiplets design/integration, RTL coding, Synthesis, CDC, timing, power analysis, system/IP verification, Silicon Bring up. Proven track record of leading the design and development of complex IPs, sub-systems, chiplets for SOCs in the multiple domains like PCIE, USB, UCIE, ARM/x86 CPUs, RISC-V, VPU/NPU, GPU, LSIO, NOC, Fabrics, AMBA buses, DRAM, SD/SDIO/eMMC etc. Responsible for defining the technical direction of ASIC designs and collaborating with cross- functional teams to ensure successful ASIC implementation. Demonstrated strong leadership, project timelines & resources management and team management skills, and the ability to influence the technical strategy of the organization. Familiar with ASIC verification methodologies, DFT, Physical design and board design which help in influencing cross functional teams in getting desired results. Excellent execution capabilities to handle multiple domains in multiple projects simultaneously. Delivered superior results through team collaboration and diversity of thought. Always open to learn new technologies to grow in technical breadth and depth. Managed development of multiple sub-systems and IPs designed from scratch for Intel IOT (Elkhart Lake), Edge (Reefbay), dVPU/NPU (Arrow LakeR), GPU (DMR-D), Media (MTL-D), Smart NIC (Altera NIC), Palm Ridge, Mount Morgan IPU SoCs which are executed in advanced technology nodes of both Intel (18A, 3nm, 5nm) and TSMC (N3e, N5, N6). Have hands on experience in chiplets, Sub-systems and IP development (micro-architecture development, 3rd party IP integration (Synopsys, Verisilicon. SiFive RISCV, ARM cores etc.,), RTL implementation, synthesis, static timing analysis, Power analysis, system/IP level verification, FPGA emulation, Si bring-up) and SoC integration flows and methodologies. Led 30+ engineer design team and have good experience in working with cross-functional teams and cross BU teams across multiple geos, resulting in good collaboration and accelerated time to market. Led IP development (RTL design, Lint, CDC, Synthesis, timing, unit level and system level verification) of various IPs in Nvdia Tegra SoC processors (from first generation [APX] to ninth generation [Xavier]) and Cisco NIC chips. Have good working experience on low power design methodologies (clock gating, power gating, multi-vt and DVFS) used in mobile SoCs. Designed couple of modules in Tegra SoC like DMA engine, SD/SDIO/ eMMC5.2 host controller and bus-bridges for Nvidia proprietary buses. Worked on architecture, micro architecture, RTL design and timing analysis. Familiar with automotive electronics ISO26262 safety requirements. Was Executive member from Nvidia in SD card org and JEDEC (eMMC) forum. Participated in SD/SDIO4.x, SD host4.x and eMMC5.x specification development. Working experience with cross functional teams like back end, analog I/O pad and SW teams to ensure IP requirements are met at each stage. Have working experience in developing tree build and regression infrastructure. Have hands on experience in ASIC verification also - Test Planning, Develop Directed, Random and System-level (soc level) Test Cases; Design Test Bench using System Verilog; Develop Random Test environment; Execute Code Coverage & Analyse Reports, Execute Gate-level Simulations; Execute Functional & Regression Tests. Good Team Player: Participated and lead the effort of SD4.x/eMMC5.x host controller design and verification. Detail oriented go- getter with Fast Learning Curve and strong analytical, decision making, problem solving, visualizing, negotiating, communication & interpersonal skills. Mentored engineers, designed IP/SS schedules with proper staging plan with cross team dependencies, identified and solved technical issues, and ensured development of high-quality products.

About The Role Solid Experience in DFT Architecture. The candidate should have experience with ATPG, JTAG, BSCAN, BIST and MBIST flows. Experience on Hierarchical DFT techniques using Pattern Retargeting in Tessent flow Strong knowledge of the Tessent Shell environment and Tessent tools The desired candidate must have specific emphasis on the following tools Test Kompress / Fastscan ATPG, MBIST, Boundary scan. Hands on experience in simulating scan patterns and debugging pattern mismatches during verification process Experience in helping to debug failing scan patterns on the ATE is highly desirable. Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys) Must be able to simulate and debug MBIST testbenches. Ability to come up with a detailed test plan based on the Arch specs Should be knowledgeable in all SOC functions such as Digital design, STA, Synthesis, PnR, DV and ATE test. The candidate should have prior experience in managing and developing teams Required Qualification B.E / B.Tech / M.E / M.Tech in Electrical / Electronic Engineering. experience-10-16 years Preferred experience of handling 10+ team members. Good understanding and exposure to SoC design and architecture Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects Comfortable with VCS / Verdi and excellent debugging skills Logical in thinking and ability to gel well within a team and be a proactive member of the team. Good communication and leadership skills Excellent team player High Integrity Job Type Full Time Job Location Hubballi

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency for today's AI platforms! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What You Will Be Doing Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff. Take part in top level floor plan and clock planning. Optimize, together with CAD signoff flows and methodologies. Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency. What We Need To See B.SC./ M.SC. in Electrical Engineering/Computer Engineering. 3-8 years of experience in physical design and STA Proven experience in RTL2GDS and STA design and convergence Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.) Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required. Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! JR1995153 Show more Show less

Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore A US based well-funded product-based startup looking for Highly talented Senior Physical Fri, Mar 28 at 9:39 AM Principal / Staff IP/RTL Design Engineer (AI Accelerator) – Multiple positions - Hyderabad Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures. We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to: Key Responsibilities Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL. Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure. Optimize design for power, performance, and area (PPA). Interface with physical design and DFT (Design for Test) engineers for seamless integration. Drive design reviews, write design documentation, and support post silicon bring-up/debug. Minimum Qualifications B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience. Previous experience in either high performance processor design or AI accelerator design is plus. Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts. Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design. Proficiency in Verilog/SystemVerilog and simulation tools. Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Key Information: Location: Embassy 247 IT Park, Vikhroli, Mumbai Workplace type: Hybrid Experience level: 6-8 years Core Skills : Technical Product management for IoT/Smart Sensor domain About Freespace (afreespace.com): We’re a workplace technology company helping organizations to achieve three key outcomes: • Right size, right design: Enabling informed decisions using real-time data to achieve portfolio optimization and the right workplace design • Smart building automations: Streamlining processes by simplifying complex seating requirements and through occupancy-driven control and automation • Exceptional employee experiences: Maximizing the benefits of the office by providing employees with the tools to find and reserve spaces, connect with each other and enjoy optimal working conditions To achieve these outcomes, we provide an integrated platform that delivers actionable workplace intelligence, through a real-time analytics platform, workplace sensors, employee experience app, signage and space management solutions. We have recently been recognized with a nomination for the IFMA New York Awards of Excellence in the Sustainability category, underscoring their achievements in fostering adaptive, efficient, and sustainable work environments. About Role: As a Technical Product Owner for the Smart Buildings team, you will play a key supporting role to the Product Manager, ensuring that the product vision and roadmap for our sensor and automation solutions are clearly translated and aligned with engineering teams. You will contribute to the development and be responsible for tactical execution-managing the product backlog, defining user stories, and ensuring technical requirements are met. Your role is pivotal in bridging business objectives with technical delivery, ensuring the successful implementation of smart building products. Key Responsibilities Collaborate closely with the Product Manager to understand and contribute to the product vision, strategy, and roadmap for smart building hardware and automation solutions. Translate high-level product goals and features into actionable user stories, technical requirements, and acceptance criteria for the engineering teams. Create, refine, and prioritize the product backlog, ensuring clarity and alignment with both business objectives and technical feasibility. Serve as the primary liaison between the Product Manager, Business Analyst, and engineering teams, facilitating clear communication and resolving ambiguities in requirements. Support sprint planning, backlog grooming, and release planning in coordination with the Technical Project Manager (TPM) to ensure timely and high-quality delivery. Monitor progress, remove blockers for the engineering team, and provide ongoing support to ensure features are delivered as intended. Ensure developed solutions meet acceptance criteria and are aligned with client needs and the overall product vision. Gather feedback from stakeholders, analyze product performance data, and recommend improvements for future iterations. Stay informed about industry trends in smart building technology, IoT sensors, and automation to inform backlog priorities and technical decisions. Collaborate with Operations and Support teams to address technical issues and ensure smooth product onboarding and customer satisfaction. Required Skills & Experience 5+ years’ experience in Agile Scrum environments, ideally as a Product Owner or Business Analyst in technology or platform-focused teams. Deep technical understanding of IoT sensor hardware , including: Circuit Design and hardware technologies (e.g., microcontrollers, thermal imaging sensors, analog/digital signal processing). Lower-level algorithmic understanding for sensor data acquisition, filtering, and calibration. Ability to read and understand firmware coding languages such as C, Python, Squirrel, and familiarity with embedded software development and debugging. Good understanding of manufacturing and factory processes , including: Design for manufacturability (DFM) and design for testability (DFT). Familiarity with PCB assembly, SMT processes, and end-of-line testing. Experience working with contract manufacturers, understanding of quality control, yield improvement, and root cause analysis for hardware issues. Experience driving device testing : Parametric testing (electrical, thermal, mechanical parameters). Field testing and simulation set-ups to validate device performance under real-world and edge-case scenarios. Ability to define test cases and acceptance criteria for hardware and firmware validation. Understanding of cloud data pipeline technologies used for device data reporting and analytics, including data ingestion, transformation, and storage (e.g., AWS IoT, Azure IoT Hub, MQTT, REST APIs). Knowledge of LoRaWAN and other wireless communication protocols relevant to smart building sensor networks. Familiarity with building automation systems and integration protocols (e.g., BACnet, ModBus, KNX). Proven ability to translate business requirements into actionable user stories and technical tasks for hardware and software teams. Excellent communication and stakeholder management skills , with the ability to bridge gaps between business and engineering teams. Strong analytical and problem-solving skills , with attention to detail and a proactive approach to identifying and resolving issues. Self-motivated, adaptable, and able to manage multiple priorities in a fast-paced environment. MBA or equivalent business qualification is preferred. Additional Technical Skills (Preferred): Experience with sensor calibration, environmental testing, and compliance standards (e.g., CE, FCC). Familiarity with device provisioning, OTA firmware updates, and device lifecycle management. Exposure to cybersecurity concepts as they relate to IoT devices and data privacy. Behaviours & Mindset Solution-oriented and curious, with a drive to understand and solve technical challenges. Collaborative and inclusive, fostering teamwork across functions. Highly organized, detail-focused, and able to manage competing priorities effectively. Clear communicator, able to simplify complex technical concepts for diverse audiences. Why Join Freespace Smart Buildings? Work at the forefront of smart building innovation, shaping sensor and automation solutions that transform workplaces. Collaborate with a passionate, entrepreneurial team driving real-world impact. Hybrid working flexibility and a supportive culture focused on career growth and continuous learning. Competitive benefits, including paid leave, health coverage, bonus schemes, and funded training. If you are ready to help deliver the next generation of smart building solutions, apply now via LinkedIn or send your CV to shivani.jindal@afreespace.com Show more Show less

Job Description New Product Development Test Engineer in Individual Contributor Role This position offers a great opportunity to work on industry leading semiconductor devices, targeted for broad applications in Automotive and Industrial markets. In this role, you’ll be a member of New Product Development team, tasked to work on new product development from design inception to manufacturing release. You will work in a cross-functional team, to drive low-cost test solutions for complex Analog / Mixed Signal ICs, using Advantest and Teradyne ATE platforms. Knowledge and experience with software development using of C++ / C / Python / JAVA is necessary. Candidate should know ATE platform architecture and programming language to develop low level ATE code for Analog / Mix Signal blocks. End goal is to design and productize deep Analog and Mix Signal test automated solutions, enabling organization benchmarks in quality, efficient code, and test-cost goals. As a member of Product & Test Engineering Team, you will own, participate, lead, and drive below activities: L1-LK1 Responsibilities Primary responsibilities: Define product DFT and test requirements Pre-PG including: a) DfT-max Requirements for a new product b) translate PRD / MRDs into PTS / SCMs / PRPs for ATE test-plan definition c) design ATE HW for lowest cost solution (max multi-site, lowest pin-mux) for Si bring-up and validation Post-Si bring-up and validation of all functional and test features. This includes extensive debug that will require good knowledge of IC design and semiconductor physics, with ability to clearly isolate and root-cause issues to design margins and/or sensitivies to wafer-fab process and parametric parameters. Execute design-of-experiments with process window corner lot to establish spec compliance of each product across full wafer-fab process window. Execute qualification cycles for Si and package to automotive, industrial, and commercial standards (as per the primary product market) During these various stages of Post-Silicon validation, you will interact with various cross-functional teams such as Design, DfT, Design Validation, Program Management, QRE/CQE, and Bench Characterization and Apps development teams Will actively own or be part of a team that owns ATE Test Solutions, including HW design, socket design, ATE Resource Allocation, Board Schematic, Layout, and Diagnostic code Will own product from bring-up to RTM (~12-14mo) and also own all the Product Entitlement goals and critical metrics for a successful ramp The candidate, in this role, is expected to lead and assist in defining and writing up test-specs for automation as well as STML (standard test methods library) to be used across multiple ATE tester platforms. Document gaps, lessons learned, and best practices with Design DFT teams to address on future products L1-LK1 Qualifications BSEE with minimum 1-5yrs of direct experience of Test & DFT Design knowledge Good programming skills using C/C++, Perl, Python Excellent communication and leadership skills, working with cross-functional teams across multiple different internal development and factory sites Excellent interpersonal skills – energetic, motivated, and self-driven Demonstrate ability to work well within a global team environment with minimal supervision Outstanding written and verbal communication skills Strong organizational skills; demonstrate ability to manage multiple tasks L1-LK1 About Us onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. More details about our company benefits can be found here: https://www.onsemi.com/careers/career-benefits About The Team We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work. Show more Show less

Electronic Components / Semiconductors Full-Time Job ID: DGC00383 Noida, Uttar Pradesh 3-8 Yrs ₹4.5 - ₹10.5 Yearly Role Description This is a full-time on-site role for DFT Engineer at Incise Infotech Pvt. Ltd. DFT Engineer will be responsible for developing, implementing, and verifying the Design for testability (DFT) on complex system on chips (SOCs). The role also involves working with the physical design team to ensure the DFT requirements are met and with the verification team to ensure the DFT design is meeting the test coverage metrics. The ideal candidate will have experience in SOC level DFT techniques, ATPG, MBIST, JTAG, and boundary scan. Qualifications Bachelor's or Master's degree in Electrical/Electronics Engineering or equivalent 3+ years of experience in DFT domain Expertise in DFT methodologies - scan insertion, scan compression, boundary scan, and memory BIST Experience in DFT tools like Tessent, ATPG, MBIST, and JTAG Experience in the complete scan chain flow (ATPG, simulation, and test pattern generation) on complex SOCs Knowledge of STA, LEC, and physical design aspects related to DFT Experience in Shell/Perl/Tcl and other scripting languages Good communication skills and the ability to work well in a team environment

Primary Skills: Altium-Intermediate, Cadence Allegro-Expert, AutoCAD-Intermediate, PCB Design-Expert, Electrical Engineering-Intermediate Contract Type: Full time opportunity Location: Pune Job Summary We are seeking a skilled Electrical CAD Designer for our Pune office to lead the design and execution of PCBAs from initial schematic to final Gerber generation and electrical drawings. This role involves intricate involvement in the complete PCBA design cycle, ensuring adherence to specified standards and customer requirements. Ideal candidates will excel in a dynamic environment, bringing innovation and efficiency to our Electrical CAD team. Key Responsibilities Design of Printed Circuit Board Assemblies (PCBAs) utilizing Cadence Allegro and Altium. Transition of PCBAs from schematic to Gerber stage, inclusive of layer stack-up and analyses for DFA, DFM, and DFT. Adaptation and modification of PCB designs based on customer specifications and compliance with all relevant standards. Creation and maintenance of electrical blueprints, including wiring harnesses and connectors using AutoCAD. Compilation and ongoing management of BOMs within the product file database. Must-Have Skills: Proven expertise in multilayer PCB design. Proficiency in Cadence Allegro. Strong foundational knowledge in Electrical or Electronics Engineering. Industry Experience: Previous experience in electronics or electrical engineering field, specifically within PCB design, is essential. A diploma in Electrical or Electronics Engineering from a premier institution in India is required, alongside 3 to 8 years of relevant work experience. ABOUT AKRAYA Akraya is an award-winning IT staffing firm consistently recognized for our commitment to excellence and a thriving work environment . Most recently, we were recognized Inc's Best Workplaces 2024 and Silicon Valley's Best Places to Work by the San Francisco Business Journal (2024) and Glassdoor's Best Places to Work (2023 & 2022)! Industry Leaders in IT Staffing As staffing solutions providers for Fortune 100 companies, Akraya's industry recognitions solidify our leadership position in the IT staffing space. We don't just connect you with great jobs, we connect you with a workplace that inspires! Join Akraya Today! Let us lead you to your dream career and experience the Akraya difference. Browse our open positions and join our team! Show more Show less

Hiring For Leading MNC Job Description To work on various phases of SoC DFT-related activities Working with the Physical Design & STA team for DFT mode timing closure Involve direct interaction with external customers Experience with either Mentor Graphics or DFT tools (Tessent Shell) is highly desirable. Desired Profile In-depth knowledge of DFT concepts Strong problem-solving & debugging skills are a must Expertise in scripting languages such as Perl and Shell. Worked on DFT insertion & verification, pattern generation, coverage improvement Show more Show less

Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization. What you will do: Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology. Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies. Good understanding of different CTS strategies and providing the feedback to Implementation Team. As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work. STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows. Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Good scripting skills (TCL/SHELL/PERL/Python) is a MUST Who you are: You are an ASIC engineer with 6+ years of related work experience with a broad mix of technologies including: All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation approach, Timing closure, physical convergence. Power Integrity Analysis Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies. Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies. You should also have hands on experience with the following Tool sets Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2 Synthesis Tools: Synopsys DC/FC Formal Verification : Synopsys Formality and Cadence LEC Static Timing verification: Primetime-DMSA Power Integrity : Apache Redhawk Physical Design Verification Synopsys ICV, Mentor Calibre Scripting: TCL, Perl is required; Python is a plus Bachelor's degree in Telecommunications Engineering, Computer Science, MIS, or related experienceWe are looking for high achievers who love challenging environment to join our team. We Are Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference. Here’s how we do it. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (30 years strong!) and only about hardware, but we’re also a software company. And a security company. An AI/Machine Learning company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box! But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.) Day to day, we focus on the give and take. We give our best, we give our egos a break, and we give of ourselves (because giving back is built into our DNA.) We take accountability, we take bold steps, and we take difference to heart. Because without diversity of thought and a commitment to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Show more Show less

Greetings from Mirafra Technologies! We are actively hiring for the role of DFT Engineer at our Hyderabad location. Location: Hyderabad Experience: 3 to 5 Years Notice Period: Immediate joiners or up to 15 days preferred To proceed, please share the following details: Current CTC: Expected CTC: Notice Period: Current Location: Job Description: We are looking for experienced professionals with: Minimum 3 years of experience in ATPG coverage , including timing and no-timing simulations Strong understanding of coverage analysis Real-time experience with Hierarchical Module (HM) level ATPG setup and simulations Why Mirafra? Mirafra Technologies is a recognized leader in semiconductor design services. Our accolades include: Qualcomm "Best HWE Services Company" 2020 Qualcomm "Zenith Award" 2018 SiliconIndia "Best Company to Work For" 2016 "Most Promising Design Services Provider" 2018 Our engineers are regularly awarded for technical excellence by our global clients. Interested? Send your resume to: swarnamanjari@mirafra.com We look forward to hearing from you!

We make real what matters. This is your role. At Aprisa, we offer complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Our detail-route-centric architecture and hierarchical database enable you to accelerate design closure and achieve optimal quality of results at a driven runtime. We're excited to be working on the next-generation RTL-to-GDSII solution, and we want YOU to be a part of this innovative journey! This is the Role Drive and be responsible for the design and development of various pieces of the RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. Guide and lead others toward successful project completion by innovating and implementing powerful solutions. Collaborate with a hardworking team of experts. Must-Have Requirements B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college with 5- 8 years of experience in software development. Validated understanding of C/C++, algorithms, and data structures. Demonstrate excellent problem-solving and analytical skills. Lead and encourage the team with your expertise. Great to Have Experience in: You will have the opportunity to develop RTL synthesis tools and work with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Additionally, you will design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly valued, as well as your proficiency in using scripting languages like Python and TCL.

Looking for Siemens EDA ambassadors This is your role. At Aprisa, we offer complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Our detail-route-centric architecture and hierarchical database enable you to accelerate design closure and achieve optimal quality of results at a driven runtime. We're excited to be working on the next-generation RTL-to-GDSII solution, and we want YOU to be a part of this innovative journey! This is the Role Drive and be responsible for the design and development of various pieces of the RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. Guide and lead others toward successful project completion by innovating and implementing powerful solutions. Collaborate with a hardworking team of experts. Must-Have Requirements B.Tech or M.Tech in CSE/ EE/ ECE from a reputed engineering college with 8-12 years of experience in software development. Validated understanding of C/C++, algorithms, and data structures. Demonstrate excellent problem-solving and analytical skills. Lead and encourage the team with your expertise. Great to Have Experience in: You will have the opportunity to develop RTL synthesis tools and work with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Additionally, you will design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly valued, as well as your proficiency in using scripting languages like Python and TCL.

Join Our Aprisa Team! Looking for Siemens EDA ambassadors Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. We make real what matters. This is your role. At Aprisa, we offer complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Our detail-route-centric architecture and hierarchical database enable you to accelerate design closure and achieve optimal quality of results at a driven runtime. We're excited to be working on the next-generation RTL-to-GDSII solution, and we want YOU to be a part of this innovative journey! This is the Role Drive and be responsible for the design and development of various pieces of the RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. Guide and lead others toward successful project completion by innovating and implementing powerful solutions. Collaborate with a hardworking team of experts. Must-Have Requirements B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college with 5-8 years of experience in software development. Validated understanding of C/C++, algorithms, and data structures. Demonstrate excellent problem-solving and analytical skills. Lead and encourage the team with your expertise. Great to Have Experience in: You will have the opportunity to develop RTL synthesis tools and work with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Additionally, you will design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly valued, as well as your proficiency in using scripting languages like Python and Tcl. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. #LI-EDA #LI-HYBRID

ATE Test Engineer for highly integrated RF SoC Integrated Circuits(ICs) for Wireless connectivity devices on UFlex tester platforms. Job Description In your new role you will: Develop Automated Test Equipment(ATE) test solutions for highly integrated RF SoC Integrated Circuits(ICs) for Wireless connectivity devices on UFlex tester platforms. Interface with cross-functional Design, DFT, PMU, RF, and DVT teams to develop and present test plans. Debug and design the required hardware and test programs that are to be used for device characterization, qualification, and production. Cooperate with Partner and Product Engineering Teams for production characterization and reliability testing. Optimize test times and yields of the Final Test Program for both FE and BE production releases. Your Profile You are best equipped for this task if you have: A bachelors degree (or foreign equivalent) in Electrical Engineering, Electronics Engineering, or a related field. 6 years of experience in ATE test program development for SoC microcontroller-based RF devices. Must have experience in: ATE Platforms (UFlex is must);Version Control Systems (SVN, GIT); Scripting (PERL, PYTHON);Programming (Visual C++, C++, ECLIPSE BASED IDE ); Bench platforms (Labview, ARM Cortex-M Firmware coding, Spectrum Analyzer); and Device Technology: - IEEE 802.11ax WIFI 6/6E, BT/BLE (Bluetooth)

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work, to amplify human imagination and intelligence. As part of the CAD team, our engineers develop and support tools for all of NVIDIAs semiconductor products. They also develop in-house tools in the area of Design for Test (DFT) using C++, Python, and TCL. You will work on infrastructure and software used to test our complex semiconductor devices. Below are some of the teams activities. We are a diverse team needing someone who is not afraid of a challenge. If this is you, come join us today. What you will be doing: Be responsible for designing and managing the DevOps workflow for the software team. Provide essential software, hardware, and lab support to ensure smooth operations and resolve any critical issues. Architect highly automated and customizable design flows using software engineering and AI Code Generation with modular design and object-oriented techniques. Support development of tools using C++/Python/TCL. Work cross-functionally with DFT Methodology, Implementation, and design teams with important DFT development tasks. Implement and maintain CI/CD pipelines for DevOps processes. Manage cloud infrastructure and on-premise systems for scalable and reliable deployment. Troubleshoot and resolve system, network, and application issues. What we need to see: A BE or BTech or MTech in Computer Science, Electronics Engineering, Electrical Engineering, or equivalent experience. At least 3+ years of relevant work experience in DevOps, with a focus on CI/CD, automation, and infrastructure management. Solid programming and scripting skills in Python/C++ or TCL desired. Strong software engineering skills: software design, algorithms, and QA. Strong experience with configuration management tools like Ansible, Puppet, or Chef. Proficiency with containerisation technologies such as Docker and Kubernetes. Experience with cloud platforms like AWS, Azure, or GCP. Strong knowledge in GitLab pipelines. Familiarity with tools like Artifactory and Jenkins, which are essential for managing binary repositories and automating builds and deployments. Good understanding of build frameworks such as CMake and Meson is required. Familiarity with JIRA for project and issue tracking is good to have. Experience in providing lab software and hardware Ways to stand out from the crowd: Knowledge or experience with DFT Strong GenAI, LLM, AI Code Generation skills desirable. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking and dedicated people in the world working for us. If youre creative and autonomous, we want to hear from you! #LI-Hybrid

Principal DFT Engineer Bangalore (Hybrid ) / Hyderabad (Hybrid ) Principal DFT Engineer Full Time \ Experienced Summary Join an ambitious, experienced team of silicon and distributed systems experts as a Design For Test engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience building and deploying DFT flows for large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. Roles & Responsibilities As a member of our team, you will work with multi-functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. You will work with 3rd party IP vendors to integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a streaming scan fabric with a sequential scan compressor/decompressor You will work with DFT Solutions Vendors to port those patterns at the top-level, to implement Memory BIST interface in high performance processor IP, and to implement high-speed I/O for the logic scan test You will work with Physical Designers to validate the DFT timing constraints You will work with RTL Designers to verify test design rules You will work with Test Engineers to bring up the patterns on the ATE Automated Test Equipment You will help develop and deploy DFT methodologies for our next generation products. Key Qualifications MSEE or equivalent experience 8-13+ years of experience in DFT or related domains You will have a solid knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation Possess excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools Have good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development Strong programming and scripting skills in Perl, Python or Tcl desired Exceptional written and oral and interpersonal skills with the curiosity to work on rare challenges Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. Job Description Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. ͏ Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort ͏ Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipro’s Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc ͏ Deliver No. Performance Parameter Measure 1. Product design, engineering and implementation CSAT, quality of design/ architecture, FTR, delivery as per cost, quality and timeline, POC review and standards 2. Capability development % trainings and certifications completed, mentor technical teams, Thought leadership content developed (white papers, Wipro PoVs) ͏ Mandatory Skills: Semiconductor Integration. Experience: 8-10 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Role Description This is a full-time on-site role for DFT Engineer at Incise Infotech Pvt. Ltd. DFT Engineer will be responsible for developing, implementing, and verifying the Design for testability (DFT) on complex system on chips (SOCs). The role also involves working with the physical design team to ensure the DFT requirements are met and with the verification team to ensure the DFT design is meeting the test coverage metrics. The ideal candidate will have experience in SOC level DFT techniques, ATPG, MBIST, JTAG, and boundary scan. Qualifications Bachelor's or Master's degree in Electrical/Electronics Engineering or equivalent 3+ years of experience in DFT domain Expertise in DFT methodologies - scan insertion, scan compression, boundary scan, and memory BIST Experience in DFT tools like Tessent, ATPG, MBIST, and JTAG Experience in the complete scan chain flow (ATPG, simulation, and test pattern generation) on complex SOCs Knowledge of STA, LEC, and physical design aspects related to DFT Experience in Shell/Perl/Tcl and other scripting languages Good communication skills and the ability to work well in a team environment Interested can share resume on Shubhanshi@incise.in

Job Description: We are looking for a skilled DFT Engineer with 13 years of experience in ASIC/SoC test design. The ideal candidate will work on scan insertion, ATPG, MBIST/LBIST, and DFT verification using industry-standard tools. Key Skills: DFT implementation: Scan, MBIST, LBIST, Boundary Scan Tools: Tessent, DFT Compiler, Tetramax, Modus Scripting: Python, Perl, Tcl Good understanding of STA and RTL flows Strong debugging & communication skills.

MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Computing and Graphics group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. RTL/Integration- Design Engineer The Person: If you have experience developing RTL for IP or subsystems and understand architectural specifications, this role is for you. You will be responsible for IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. Key Responsibilities: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up Lead a subsystem development team of 4 to 5 members. Preferred Experience: 5-7 years full-time experience in IP hardware design Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Verilog lint tools (Spyglass) and verilog simulation tools (VCS) Clock domain crossing (CDC) tools Detailed understanding of SoC design flows Understanding of IP/SS/SoC Power Management(PM) techniques Power Gating, Clock Gating Experience with embedded processors and data fabric architectures (NoC) Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1 Benefits offered are described: AMD benefits at a glance .

We are looking for Industrial Painter, Spray Painter with relevant experience in sheet metal industry for metal surface - Primer & Paint with the help of air machine. Understands WFT & DFT Job Types: Full-time, Permanent Pay: ₹15,000.00 - ₹18,000.00 per month Schedule: Day shift Morning shift Night shift Rotational shift Supplemental Pay: Overtime pay Shift allowance Location: Noida, Uttar Pradesh (Required) Work Location: In person Expected Start Date: 19/05/2025

Role & responsibilities Design and develop printed circuit boards (PCBs) based on project requirements. Create schematic diagrams and translate them into PCB layouts using CAD software. Collaborate with cross-functional teams such as electrical engineers and product designers to ensure the PCB meets design specifications. Optimize PCB layout for signal integrity, power distribution, and thermal management. Perform design rule checks (DRC) and electrical rule checks (ERC) to verify design accuracy. Component Footprint/Landpattern modification and selection. Work with manufacturers to ensure that the PCBs are fabricated and assembled correctly. Troubleshoot and resolve issues during the prototype testing phase. Ensure compliance with industry standards and regulations, such as IPC standards and RoHS guidelines. Continuously improve designs for cost reduction, performance enhancement, and manufacturability. Maintain design documentation and version control for all PCB designs. Provide technical support and recommendations for board assembly and testing. Stay up to date with emerging technologies and design techniques in the PCB industry.

Urgent Hiring: Paint Shop Head Responsibilities and Duties: o Knowledge of having sheet metal fabrication o Oversee pre-treatment processes for liquid/PU painting and powder coating operations. o Manage bath preparation and monitor its parameters to ensure quality outcomes. o Conduct chemical titration testing to verify chemical compositions and efficiency. o Perform various testing standards including adhesion, impact, bend, salt spray test (SST), and dry film thickness (DFT) to ensure products meet quality specifications. o Understand and implement the IATF (International Automotive Task Force)/ISO 90001 process audit requirements within the coating operations. o Manage and maintain all coating equipment to ensure optimal performance and minimize downtime. o Implement and maintain 5S methodology to promote an organized and efficient workspace. o Efficiently manage manpower, allocating resources effectively to ensure smooth and uninterrupted operations. o Lead a team of operators and technicians, fostering a culture of safety, quality, and continuous improvement. Qualifications and Skills · Minimum diploma/ graduation in BSc or chemical Eng. · Minimum experience 8-12 years in liquid painting & powder coating process. · Proficient in MS office. · Handling the skills of manpower and leadership. Familiarity with IATF/ISO 90001 standards and quality testing methods. Excellent organizational and leadership skills. Knowledge of 5S principles and practices. Salary: INR 40,000 to 55,000 per month, based on experience Job Type: Full-time Pay: ₹25,000.00 - ₹40,000.00 per month Benefits: Health insurance Work Location: In person