2364 Dft Jobs - Page 40

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position: Principal Software Engineer Grade: T4 Location: Noida Job Responsibilities: The role’s day to day responsibilities cover: R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the...

Key Responsibilities: Perform surface preparation including scraping, sanding, hydro-jetting, and grit blasting to achieve required finish Apply primer, anti-corrosive, and topcoat systems using brush, roller, or spray techniques as per naval specifications Conduct painting of underwater hulls, topside areas, weather decks, tanks, bollards, guard rails, and fittings Ensure DFT (Dry Film Thickness) Handle non-skid coatings , enamel finishes, and specialized marine paints Maintain cleanliness and safety of work areas, tools, and PPE Assist in erection and dismantling of scaffolding and containment systems Document work progress and submit reports to supervisors Skills & Qualifications: PCC / P...

Location: Remote Experience: 7+ years About the Role Mandatory Skills: RTL, Coding, Design, IP Design, SoC Development, Lint, CDC, Micro Architecture – Mandatory PCIe/DDR/Ethernet – Any One I2C, UART/SPI – Any One Spyglass Lint/CDC / Synopsys Lint/CDC / Verdi/Xcellium – Any One Scripting languages like Make, Perl, Shell, Python – Any One Good to Have: Processor architecture / ARM debug architecture Debug issues for multiple subsystems Create/review design documents for multiple subsystems Able to support physical design, verification, DFT and SW teams on design queries and reviews Details JD: Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integra...

This position is posted by Jobgether on behalf of Alphawave IP inc. We are currently looking for a Staff Engineer - STA in India. In this role, you will play a key part in driving timing convergence for complex SoCs, ensuring high performance and reliable tape-outs across advanced technology nodes. You will collaborate with cross-functional teams, contribute to methodology development, and manage timing closure for multi-mode and multi-corner designs. This position offers the opportunity to lead impactful engineering projects while working in a flexible, collaborative environment that values innovation, precision, and professional growth. Accountabilities As a Staff Engineer - STA, you will:...

We are looking for a Senior PCB Designer who will lead the design of compact, high-performance PCBs for hearing aids and charging cases and other audiological equipment in the future. The ideal candidate will have deep expertise in PCB design and layout, and the ability to write basic firmware to bring up and test their hardware designs. Key Responsibilities PCB Design & Development (Primary Focus) Design multilayer, rigid-flex PCBs optimized for miniaturized medical devices (hearing aids, charging cases). Convert hardware schematics into high-quality PCB layouts under strict size, power, and thermal constraints. Apply best practices for low-noise, low-power, and high-reliability design, inc...

You will be responsible for executing internal projects or small tasks within customer projects related to VLSI Frontend, Backend, or Analog design with minimal supervision from the Lead. Your role will involve working as an Individual contributor on tasks such as RTL Design, Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will be expected to analyze and complete assigned tasks within the defined domain successfully and on time with minimal support from senior engineers, ensuring quality delivery as approved by the senior engineer or project lead. Quality of deliverables is a key focus, requiring clean delivery of modules that are easy to...

Job description: Senior Electronics and Embedded Engineer – Environmental IoT Devices (Sensors, Compliance & Future-Ready Development) Location: Coimbatore, India | Type: Full-time (On-site) Compensation: Up-to 8 LPA + ESOPs, health insurance About Carbelim Carbelim is an IIT-Madras and IIM-Lucknow backed climate-tech start-up pioneering nature-based carbon capture solutions using advanced microalgae photobioreactors. Our AI-driven systems purify polluted air, capture CO₂, and transform emissions into valuable bio-based products. As a climate-tech company, our products are centred around air and water environmental monitoring , where precision, reliability, and long-term stability are critic...

You have an exciting opportunity as a DFT Lead with Synopsys Tools in Bangalore. With over 10 years of experience in DFT, you are well-versed in all aspects including SCAN/ATPG, MBIST, and Boundary Scan. Your expertise lies in DFT logic integration and verification, along with debugging low coverage issues and DRC fixes. You have hands-on experience in gate-level ATPG simulation with and without timing, as well as pattern generation, verification, and delivery to the ATE team. Post silicon, you excel in debug and support on failing patterns, ensuring smooth operations. Your proficiency in tools like TestMAX from Synopsys is commendable. You have a knack for developing and automating flows an...

Job Summary: A technically proficient and detail-oriented Aerospace Valve Assembly and Testing Engineer to handle the end-to-end process of assembling, testing, and qualifying aerospace valves. The ideal candidate will also be responsible for conducting environmental tests as per MIL-STD requirements, ensuring all assemblies meet aerospace and defense compliance standards. Key Responsibilities: 1. Valve Assembly: Assemble aerospace-grade valves (e.g., solenoid, relief, check, control valves & Regulator) per engineering drawings, standard operating procedures, and customer specifications. Ensure clean handling and ESD precautions for sensitive components. Perform torquing, fitting, and sub-as...

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globa...

Job Overview: Experience: 3 15 years Responsibilities: Verification engineer with a knowledge of IP verification or SoC integration verification Experience in SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx integration verification in SoC RTL. Experience in architecting and implementing SV/UVM testbenches, create and maintain reusable verification components Experience in formal verification strategy for complex IP blocks defining properties, driving proofs and coverage closure Your key responsibilities will include writing test plans, defining test methodologies, SystemVerilog/Verilog testbench development, developing UVM or C based software tests, and debugging of ...

Good working experience in Python, C/C++, Shell/Bash and other scripting languages Experience in developing CI/CD using Jenkins, Git or other SCM tools Work experience in Selenium Web automation, django, dashboards, database management and related web development platforms Working experience in integrating Jira and Confluence Automation of ASIC Development Flows & Pre-Silicon Platforms development for productivity improvement & quick delivery to FW, ASIC Validation & ASIC Verification/DFT Customers. Knowledge in Devops and work experience interacting with IT team for developing, integrating and deploying test automation infrastructure Experience in Jenkins job parallelization, manage virtual...

The Role: This position is an excellent opportunity for a hard-working RTL design engineer looking for a fast-paced role employing the latest hardware design and verification methodologies to develop complex and highly configurable hardware IP that sit at the heart of Arm-based Systems. Working as the System IP team and engaging with the world s most famous technology companies, we are driving innovation into all areas that compute is possible to help us build better solutions for the billions of people using our technology worldwide. The team owns the creation of a range of popular Arm IP, like Interconnects/NoCs, MMUs and ISPs used in multiple innovative products targeting high-end network...

: Arm s Solutions group DFT team implements DFT for test-chips and hard-macros to prove Arms soft IP power, performance, area, and functionality within the context of a SoC using the latest DFT techniques and process technologies. We closely collaborate with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE. Responsibilities: Architect, Implement, and validate innovative DFT techniques on test-chips and hard-macros. Insert DFT logic into SoC-style designs at the RTL level and at the Synthesis gate level, validate all features, an...

: Arm s Solutions group DFT team implements DFT for test-chips and hard-macros to prove Arms soft IP power, performance, area, and functionality within the context of a SoC using the latest DFT techniques and process technologies. We closely collaborate with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE. Responsibilities: Architect, Implement, and validate innovative DFT techniques on test-chips and hard-macros. Insert DFT logic into SoC-style designs at the RTL level and at the Synthesis gate level, validate all features, an...

Responsibilities As a creative design engineer with a knowledge of subsystems and SoCs you will be part team developing Subsystems & SoCs. You will work with Architects to capture the requirements and develop Micro-architecture specifications for one or more SOC areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc. Key responsibilities will include writing micro-architecture and work with Design team to deliver high quality RTL. Collaborate with verification and Validation team to review test plans, and help debug design issues. Closely work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA. Contr...

If you are passionate about pushing the boundaries of Design technology and thrive in a collaborative, dynamic environment, we invite you to join our team as a Design Engineer. Join us to be part of our journey in shaping the future of SoC design and innovation. Responsibilities As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team integrating IP and developing logic for SoCs. You will work with the project team to understand and review the architecture and develop the design specifications. Your key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks. You will wo...

About Marvell . Your Team, Your Impact This position is with ASIC design physical implementation (PD) team part of Central Engineering business unit at Marvell, Bangalore. This team as part of global Implementation team that plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s. We are looking for strong technical leaders in the domain of physical design having Full-Chip implementation experience on hierarchical designs using industry standard tools. #LI-LP1 What You Can Expect Should be able to independently handle every aspect of physical design. Should be able to direct junior engineers into execu...

PMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Computing and Graphics Group, you will help bring to life cutting-edge designs. You will lead a front-end design and integration team, working closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: The ideal candidate will have experience leading a team to develop RTL for SoC subsystems and understand architectural specifications. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. KEY RESPONSIBLITIES: Design of IP and subsystems with integration of AMD a...

[{"Salary":null , "Remote_Job":false , "Posting_Title":"Principal Engineer- DFT" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Lead the DFT implementation of a complex SoCs Work hands-on critical tasks as and when needed Own the DFTimplementation flows, methodologies, and execution of SoCs \u25E6 \uFEFF\uFEFFExperience in all phases ofthe DFT pre- and post-Si for large SoCs \uFEFF\uFEFFImplement DFT ofSoC/Full-chip-level and/or high-speed cores/blocks \uFEFF\uFEFFExperience inhigh-speed, low-power, mixed-signal SoCs is a plus \uFEFF\uFEFFPreferably worked on5nm/7nm/12nm/14nm/16nm nodes at the major foundries \uFEFF\uFEFFExperience indeveloping DF...

Job Overview Arm s DFT methodology team works on DFT flows and methodology for projects, including soft IP, hard macros, SOCs and physical library IP across all the Arm design sites. In addition, this team builds and drives DFT methodology and flows throughout all of Arm and works to get support from EDA vendors to support our methodologies. Responsibilities: Support DFT on multiple types of projects in multiple design centers and apply innovative DFT techniques and affect the content of forthcoming CPU, GPU, ML and systems IP, SOCs some years before they appear in mainstream products. This candidate will contribute to DFT methodology by crafting flows, evaluating tool capabilities, helping ...

Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation. Required Skills and Experience : This role is for a Senior Principal DFT Engineer with proven ability in Design for Test Experience coding Verilog RTL, TCL a...

As a part of in Arms Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. Responsibilities: Timing analysis and closure responsibilities at SoC level as well as block/subsystem level Review of timing QOR at every execution milestones and supervising to meet required guideline for smoother closure ECO planning, generation and tracking to closure by collabor...

Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation. Required Skills and Experience : This role is for a Principal DFT Engineer with proven ability in Design for Test Experience coding Verilog RTL, TCL and/or P...

In Arms Solutions Engineering group, our primary focus extends beyond the development of advanced System-on-Chips (SoCs). In the endeavour to deliver a quality silicon we need to ensure all our signoff checks across various domains are diligently performed. Delivering quality silicon leads to quality rewards and every effort and skill is recognized and appreciated at ARM. Our responsibilities also encompass improvising methodologies, influencing EDA tools and build a knowledge base which will help in our product design. Learning and sharing knowledge is part of ARM culture and is very much appreciated and encouraged. If your interested in working with a team of collaborative and smart engine...