Lower Power Sign off- Staff Engineer

Responsibilities:

• Setting up and running Logic Equivalence check which is of signoff quality.
• Analyzing low power results and signing off on the structural checks run using Conformal Low Power. Provide feedback to relevant teams to ensure successful closure of blocks on time.
• ECO is part of every silicon now a days and the engineer needs to own up generating functional ECO for quick closure
• Collaborate with RTL, Synthesis and PnR implementation team to successfully close on different hard macros
• Work with methodology team to improve the flow
• Develop automation using python/perl/tcl scripting to avoid repetitive tasks and thus improve your work life balance
• Supporting and enabling other sign-off team members to attain efficient and quality outcomes

Required Skills and Experience:

• Bachelors/Masters with 3-5 years of minimum experience in Logic Equivalence check (Formality / LEC) and Low power (VCLP / CLP)
• Values communication as a key medium to nurture learning, builds trust with others and solves sophisticated problems with dependencies.
• Strong understanding in RTL coding (SystemVerilog, Verilog & VHDL) and RTL for Synthesis
• Good understanding of the concepts related to Low power synthesis, place & route, DFT.
• Should be proficient in any of the scripting or automation languages such as Python, Perl, TCL, Sed or Awk.

Nice To Have Skills and Experience:

• Working on ARM CPU and GPU designs would be added value
• Experience working on generating functional ECO using EDA tools will add value