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DFT Director

DFT Director

Intel

20 - 25 years

35 - 40 Lacs

bengaluru

Posted:2 weeks ago| Platform:

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Skills Required

version control atpg verilog dft performance management synthesis jtag sta bist scanning simulation scan insertion digital design rtl vhdl rtl design linux perl mbist vlsi system verilog tcl

Work Mode

Work from Office

Job Type

Full Time

Job Description

Job Details:
If you are a senior leader with expertise in Design for Test and are passionate about defining the future of Client and Hyperscaler designs and SoC's, Intel has opportunities for you.The Central Engineering group is responsible for delivering industry-leading Custom Silicon Solutions for Intel Customers in the Client and Hyperscaler Domains.

The DFT Director's responsibilities include (but are not limited to):

Lead the product DFT Architecture for the Intel Custom Silicon Business
Drive DFT technical readiness (TR) and define DFT strategy to meet the Intel Manufacturing requirements
Work with the team to define DFT quality control/process for SoC execution predictability and high quality DFT delivery to achieve the first-time-right goals
Improve overall product cost by analyzing product requirement to balance DFT/Manufacturing requirements vs products' PPA and cost
Support critical post-Si debug and yield/Vmin analysis as required
You would also be responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.
Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment

Qualifications:

Bachelors Degree in Electrical/Computer Engineering or related STEM degree plus 20+ years of industry experience in the following:
Expert in industry standard DFT (TAP/JTAG, MBIST, SCAN/ATPG)
Experienced in DFT product architecture/micro-architecture with end-to-end DFT design and verification flow knowledge from DFT technical readiness (TR) to product PRQ support Experienced with EDA tools such as ATPG tools, Siemens Tessent shell, VCS simulation and/or debug tools, Prime time and DFTC and/or similar tools Understand the best known method to integrate IP from internal and/or external vendors, such as IO PHY and PLL
Experienced in DFT pattern generation flow, post-Si debug and yield analysis Strong leadership and mentorship and be able to lead cross-site initiatives/WG with key stakeholders and customers

Job Type:
Experienced Hire

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DFT Director