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Design Verification Lead (Pervasive ABIST)

Design Verification Lead (Pervasive ABIST)

IBM

8 - 13 years

9 - 13 Lacs

hyderabad

Posted:23 hours ago| Platform:

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Skills Required

bist scanning design verification dft memory bist jtag c++ atpg digital design vhdl design engineering rtl design fpga tetramax rtl coding perl system verilog tcl synthesis sta python rtl verilog cadence boundary scan vlsi logic design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Understand the design specification , Memory and Memory BIST engine connections

Develop skills in IBM BIST verification tools and apply them successfully

Develop the verification environment and test bench

Debug fails using waveform, trace tools and debug RTL code

Work with Design team in resolving/debugging logic design issues and responsible for deliveries

Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise

8+ years of experience in Design Verification - demonstrated execution experience of verification of logic blocks

Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIST

Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL)

Good programming skills in C/C++, Python/Perl

Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails

Hardware debug skills backed by relevant experience on projects

Exposure in developing testbench environment, write complex test scenarios

Good communication skills and be able to work effectively in a global team environment.

Drive verification coverage closure

Preferred technical and professional experience

Knowledge of Chip-Initialisation , SCAN , BIST is a plus

Scripting Expertise backed up relevant experience in the same

Writing Verification test plans

Functional and code coverage analysis and debu

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Design Verification Lead (Pervasive ABIST)