Design Verification Engineer | Bangalore

10 years

25 - 30 Lacs

Posted:1 day ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

Mandate - Required Skillset

  • RTL Verification Experience: 4–10 years of hands-on experience verifying RTL designs for digital systems or SoCs.
  • Simulation Tools Proficiency: Expertise in using industry-standard verification tools such as ModelSim, Cadence Incisive, and Synopsys VCS.
  • Testbench Development: Proficient at developing and maintaining verification environments and testbenches using SystemVerilog, UVM, Verilog, or VHDL.
  • Functional Verification: Strong background in functional verification, writing test plans, creating test cases, debugging failures, and ensuring design quality.
  • Scripting for Automation: Experience scripting with Python, Perl, or TCL to automate verification workflows and enhance productivity.
  • Coverage Analysis: Familiar with coverage-driven verification methodologies (functional and code coverage).
  • Team Collaboration: Excellent communication and teamwork skills for efficient interaction with design and architecture teams.
  • Problem Solving: Strong analytical skills to identify, debug, and resolve complex design and verification issues.

Nice To Have

  • Experience with formal verification tools.
  • Exposure to FPGA prototyping and hardware emulation.
  • Knowledge of industry standard protocols (e.g., AXI, PCIe, USB).
Skills: systemverilog,uvm,functional verification,coverage analysis,synopsys vcs,fpga prototyping (nice to have),scripting (python, perl, tcl),verilog,simulation tools (modelsim, cadence incisive, synopsys vcs),testbench development (systemverilog, uvm, verilog, vhdl),python,formal verification tools (nice to have),vhdl,team collaboration,rtl verification,protocol knowledge (axi, pcie, usb - nice to have),modelsim,problem solving,cadence incisive,perl,tcl

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