562 Atpg Jobs - Page 6

As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6....

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC ver...

Job Details: Job Description: If you are a senior leader with expertise in Design for Test and are passionate about defining the future of Client and Hyperscaler designs and SoC's, Intel has opportunities for you. The Central Engineering group is responsible for delivering industry-leading Custom Silicon Solutions for Intel Customers in the Client and Hyperscaler Domains. The DFT Director's responsibilities include (but are not limited to): 1. Lead the product DFT Architecture for the Intel Custom Silicon Business 2. Drive DFT technical readiness (TR) and define DFT strategy to meet the Intel Manufacturing requirements 3. Work with the team to define DFT quality control/process for SoC execu...

Key Responsibilities:- DFT Architecture Definition: Develop and implement DFT architectures, including MBIST, scan insertion, and JTAG. - Test Pattern Generation: Generate test patterns and simulate with and without timing annotation. - Test Coverage Analysis: Analyze test coverage and optimize test strategies. - Collaboration: Work closely with cross-functional teams, including IC design, verification, and product engineering. - Scripting and Automation: Develop scripts for automatic scan insertion, ATPG, and pattern generation using languages like Perl, Python, or Tcl. Requirements:- Experience: 5+ years of experience in DFT, MBIST, scan insertion, ATPG, and JTAG. - Technical Skills: Profi...

Hi Tech Mahindra hiring DFT Engineers for Bangalore location. Exp: 9-14yrs Location: Bangalore NP: 0-45days JD: 1. Experience with DFT tools such as Synopsys DFT Compiler, TestKompress and Xelium 2. 7+ years of experience in DFT engineering, with a focus on Scan Insertion and ATPG, ICL, SSN 3. Strong knowledge of DFT techniques such as Scan Chains, ATPG, Boundary Scan, BIST. 4. Proficient at Pattern Retargeting, DRC Handling, coverage improvement. 5. Collaborate with RTL and physical design teams to ensure proper integration of DFT logic, including scan chains, boundary scan, and BIST Interested people share cv to Ramya.K1@techmahindra.com

Hi All, Greetings from Eximietas...! Position: Senior DFT Engineers/Leads/Architects/Managers Location: Visakhapatnam Mode of Work: On-site Exp: Min 8+ Years We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. Job Overview: Must be able to obtain and ma...

Role Overview: As a member of the Common Hardware Group (CHG) at Cisco, you will be part of a team that delivers cutting-edge silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Your work will involve designing networking hardware for Enterprises, Service Providers, Public Sector, and Non-Profit Organizations worldwide. Join the team in shaping Cisco's groundbreaking solutions by participating in the design, development, and testing of advanced ASICs that are at the forefront of the industry. Key Responsibilities: - Implement Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics requirements of the des...

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be an integral part of the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your responsibilities will include defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team that delivers cutting-edge IPs crucial for every SOC developed by AMD. Key Responsibilities: - Lead and define Design for Test/Debug/Yield Features specific to PHYs....

As a candidate for the role, you should possess a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or have equivalent practical experience. Additionally, you need to have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, including managing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial that you have familiarity with ATPG, Low Value (LV), Built-in Self Test (BIST), or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications for this position include proficiency in a programming language such as Pe...

Role Overview: As a member of our dynamic team, you will contribute to the development of custom silicon solutions that drive the future of Google's direct-to-consumer products. Your role will be pivotal in innovating products that are globally cherished, influencing the next wave of hardware experiences to deliver exceptional performance, efficiency, and integration. You will work towards Google's mission of organizing the world's information and making it universally accessible and useful, synergizing the best of Google AI, Software, and Hardware to craft profoundly beneficial experiences. The team is dedicated to researching, designing, and advancing new technologies and hardware to enhan...

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: Lead DFT Engineer THE ROLE: Lead DFT engineer will lead strong ...

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse...

We are seeking a highly experienced Senior DFT Engineer with 8+ years of hands-on expertise in developing and implementing DFT architectures for complex SoCs. The ideal candidate should have a solid background in scan insertion, ATPG, BIST, and silicon debug. Key Responsibilities: Define and implement DFT architecture for digital and mixed-signal SoCs Perform scan insertion, boundary scan, and ATPG pattern generation Integrate Memory BIST (MBIST) and Logic BIST (LBIST) Drive DFT verification and post-silicon validation/debug Collaborate with RTL, synthesis, STA, and backend teams to ensure testability Ensure high test coverage, test time optimization, and compliance with ATE requirements Req...

We are looking for Senior DFT-MBIST Engineer with 5+Yrs of relevent experience in DFT Design Responsibilities Implement/Integrate and verify DFT logic, for example, memory built-in self test (MBIST), scan chains, DFT compression, TAP controller, BSCN, iJTAG instrumentation, functional BIST, logic BIST and eFuse logic on test chips. Work with silicon engineering team to create test plans and generate test patterns Participate in post-silicon activity like bring up, diagnostics and characterization Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies. Provide support to internal teams. Scan insertion, Scan compression, Stuck-At, At-Speed test and cov...

DFT Lead - 7 to 15 Years Job Location : Bangalore| Hyderabad | Noida | Ahmedabad | Chennai (NO WORK FROM HOME OR REMOTE WORK) Job Specs: • In depth knowledge of DFT concepts • In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis • In depth knowledge and hands on experience in MBIST insertion and Memory test validation • Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations • Expertise in scripting languages such as perl, shell, etc. • Experience in RTL and Gate level simulations of scan and MBIST test vectors • Knowledge of equivalence check, ...

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwid...

Role Summary: As a DFT engineer at Alphawave Semi, you will be working on end-to-end Custom Silicon Design cycle, from DFT-architecture planning to delivering qualified Si parts to our customers. You will be using some the best industry-standard tools and Alphawave specific workflows to implement full chip level advanced Scan and MBIST insertion, verification, and pattern generation. You will collaborate closely with customers, working hand-in-hand with RTL/PD teams and supporting Test/Product Engineering teams. Role & responsibilities Develop and implement comprehensive DFT architectures, collaborating on early planning stages. Serves as the primary point of contact for DFT-related inquirie...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Hands-on experience in scan insertion, JTAG, ATPG DRC, and coverage analysis. Proficiency in simulation debug with timing/SDF Experience with LBIST and Mixed Signal Radar ICs is highly desirable. Ability to debug and root cause simulation failures

Experience: 8+ Years Location: Bangalore Notice Period: Immediate to 30 Days Serving. JD: B.E/B.Tech or M.E/M.Tech in Electronics or related field. Minimum 10+ years of hands-on experience in DFT with a strong focus on MBIST . Proficient in tools such as Synopsys DFT Compiler, Tessent (Mentor), or equivalent. Solid understanding of MBIST Insertion, scan insertion, ATPG, boundary scan, and JTAG. Experience with memory test algorithms, repair analysis, and pattern generation. Familiarity with scripting languages (TCL, Perl, Python) for automation. Strong analytical and problem-solving skills with the ability to work independently.

3-5 Years experience in DFT Experience with IJTAG is a must. Hands-on experience in scan insertion, ATPG DRC, and coverage analysis Please do share your updated resume to - dft@greensemis.com Accessible workspace Flexi working Health insurance

Principal DFT Manager Bangalore, Karnataka, India Date posted Sep 17, 2025 Job number 1874063 Work site 3 days / week in-office Travel 0-25 % Role type People Manager Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our serve...

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SOC Verification Lead T HE ROLE : As a member of the Radeon Tec...

Company: Eteros Technologies India Private Limited Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad • Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies. • Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacen...