169 Atpg Jobs - Page 6

Urgent Hiring for Lead DFT Design Engineer Experience - 5+ Years to 15 Years CTC - Upto 80LPA Location - Bangalore, Hyderabad, India Roles and Responsibilities Experience with owning chip level DFT and Post Silicon debug / analysis Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification. Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation. Understanding generation of functional patterns for ATE Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc) Design experience in MBIST / LBIST is an added advantage. Good understanding of constraints development for Physical Design Implementation / Static Timing Analysis. Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits and its design cycles is an added advantage. Effective communication skills to interact with all stakeholders. Team and People Skills: The candidate should have good people skills to work closely with the systems, analog, layout and test team Must be highly focused and remain committed to obtaining closure on project goals If interested or have any reference then call us at 9560379526 or email us at bkirad@reqres.com

Role: Senior DFT Engineer Exp: 5+ years Location: Bangalore Skills: Siemens Tessent (Memory BIST, Scan Insertion) ATPG (TetraMAX/TestKompress) Scan Compression, VTRAN TCL/Python scripting Silicon bring-up & ATE debug

Team Computers Pvt Ltd is looking for DFT Implementation Engineer to join our dynamic team and embark on a rewarding career journey. DFT Implementation Engineer is responsible for overseeing and optimizing dft implementation engineer operations. This role involves strategic planning, team coordination, and execution of tasks to ensure efficiency and productivity. The incumbent will collaborate with stakeholders to align operations with business goals. Duties include monitoring performance, ensuring compliance with policies, and implementing best practices. Additionally, they will manage resources, resolve operational challenges, and contribute to continuous improvement initiatives. Strong analytical skills, leadership abilities, and industry knowledge are essential for success in this role.

Should have strong knowledge on Computer Hardware and Windows OS. Need to have rework knowledge related to motherboard and good understanding with electronic components. Must have experience in windows. .Knowledge and experience with kernel- mode debugging using Microsoft development tools (Visual Studio, WinDBG, etc.) Engineer should have Knowledge on CPU Cores, Intel DTT, Gaming core Performance Evaluation, hyper threading. Additonal knowledge related to Intel Innovation Framework and ATPG (Automatic test pattern generator)Python Scripting will be added advantage. Must have work experience in validating various domain ( like Graphics, PM, IPU,Sensor, Wi-Fi, BT, USB,TBT ,etc). Solid background in Pre/Post Silicon validation Ability to work independently and proactively. Good problem analysis and solving skills coupled with a strong drive to learn and teach others Required skills and qualifications Basic knowledge about technologies. Good communication skills What We Offer Flexible work environment, allowing for full-time remote work globally for positions that can be performed outside a HARMAN or customer location Access to employee discounts on world-class Harman and Samsung products (JBL, HARMAN Kardon, AKG, etc.) Extensive training opportunities through our own HARMAN University Competitive wellness benefits Tuition Reimbursement Access to HARMAN Campus Fitness Centre and Cafeteria An inclusive and diverse work environment that fosters and encourages professional and personal development.

We are seeking a passionate and dynamic Lead Engineer Design for Test (DFT) to join our team. If you have extensive expertise in ATPG, SCAN, JTAG, and MBIST, and are eager to lead and mentor a talented team, this is the perfect opportunity for you! Key Responsibilities Lead and guide a team of engineers in the implementation of advanced DFT methodologies. Architect, implement, and validate DFT techniques, including ATPG, SCAN, JTAG, and MBIST, ensuring efficient and scalable design solutions. Collaborate closely with design, verification, and backend teams to deliver high-quality silicon solutions. Drive design reviews, debug issues, and ensure successful tape-out. Optimize and innovate DFT strategies for cutting-edge semiconductor designs. Required Skills and Experience 5+ years of experience in Design for Test (DFT) implementation and methodologies. Strong expertise in ATPG, SCAN, JTAG, MBIST , or at least one DFT technique with hands-on experience. Experience with industry-standard DFT tools such as Synopsys Tetramax, Mentor Tessent, Cadence Modus, or similar tools. Proven ability to debug DFT-related issues in pre-silicon and post-silicon environments. Excellent communication and leadership skills to lead and mentor a team. Proactive and adaptable with a problem-solving mindset. Preferred Qualifications Experience in SOC-level DFT implementation. Familiarity with RTL design and verification methodologies. Knowledge of silicon bring-up and testing processes. Why Join Us? Best Salary in the Market for the right candidate. Attractive bonus plan to reward your contributions. Be part of a fast-growing, innovative team driving next-generation semiconductor solutions. Opportunities to lead and shape projects with cutting-edge technology. A supportive and collaborative work environment that values your expertise and contributions. How to Apply? Please submit your application through prabhu.p@acldigital.com . For any queries, feel free to reach out me

We are seeking a passionate and dynamic Lead Engineer Design for Test (DFT) to join our team. If you have extensive expertise in ATPG, SCAN, JTAG, and MBIST, and are eager to lead and mentor a talented team, this is the perfect opportunity for you! Key Responsibilities Lead and guide a team of engineers in the implementation of advanced DFT methodologies. Architect, implement, and validate DFT techniques, including ATPG, SCAN, JTAG, and MBIST, ensuring efficient and scalable design solutions. Collaborate closely with design, verification, and backend teams to deliver high-quality silicon solutions. Drive design reviews, debug issues, and ensure successful tape-out. Optimize and innovate DFT strategies for cutting-edge semiconductor designs. Required Skills and Experience 9+ years of experience in Design for Test (DFT) implementation and methodologies. Strong expertise in ATPG, SCAN, JTAG, MBIST , or at least one DFT technique with hands-on experience. Experience with industry-standard DFT tools such as Synopsys Tetramax, Mentor Tessent, Cadence Modus, or similar tools. Proven ability to debug DFT-related issues in pre-silicon and post-silicon environments. Excellent communication and leadership skills to lead and mentor a team. Proactive and adaptable with a problem-solving mindset. Preferred Qualifications Experience in SOC-level DFT implementation. Familiarity with RTL design and verification methodologies. Knowledge of silicon bring-up and testing processes. Why Join Us? Best Salary in the Market for the right candidate. Attractive bonus plan to reward your contributions. Be part of a fast-growing, innovative team driving next-generation semiconductor solutions. Opportunities to lead and shape projects with cutting-edge technology. A supportive and collaborative work environment that values your expertise and contributions. How to Apply? Please submit your application through prabhu.p@acldigital.com . For any queries, feel free to reach out me

As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Strong background and experience with Scan design, Clock architecture, ATPG methodology and industry standard tools Worked on Test compressions and decompression scan methodology generating test patterns at block and SoC level. Worked on ATPG test pattern generation stuck-at and at-speed with depth fault coverage analysis identifying issues to meet the coverage targets. Worked on boundary Scan test plan, test coverage with JTAG Understand MBIST concepts and insertion and test the integration at partition and SoC level. Understand the concept of memory redundancy logic. Understand JTAG concepts with all jtag IEEE standards Worked on industry standard DFT tools Strong knowledge on scripting in TCL/Perl/Python. Must possess good communication skills, be a self-driven individual and a good team player

Job Description: You will be responsible for IP / sub-system level micro-architecture development and RTL coding. Prepare block/sub-system level timing constraints. Integrate IP/sub-system. Perform basic verification either in IP Verification environment or FPGA. Deep knowledge of mixed signal concepts Deep knowledge of RTL design fundamentals Deep knowledge of Verilog and System-Verilog Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Power intent, Static Timing Analysis (STA) Write design specifications for different functional blocks on a chip, Create micro-architecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code, conduct Synthesis and place and route to meet timing / area goals Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence Floorplan efforts Code Verilog RTL for high performance designs Specify, design, and synthesize RTL blocks, optimize and floorplan them

Job Description: Be a member of the team that plays a significant role in ensuring the quality of next generation processors for Smart phones and Smart card through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include Interfacing with the design teams to ensure DFT design rules and guidelines are met. Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques. MBIST verification and test pattern generation through Mentor tool. Work closely with design team on IDDQ constrains validation and pattern generation along with IVA analysis. Simulating and verifying the ATPG (SAF, TDF) and MBIST patterns on unit delay and min/max timing corners. Working with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE debug. Lead team of 2-3 engineers working bin DFT/ADFT pattern generation and validation Contribute to technical innovation, development of innovative techniques in the area of test cost reduction, simulation time reduction and quality enhancement Responsible for supporting post Si debug effort, issue resolution Developing, enhancing and maintaining scripts as necessary. Skills: Minimum of 8 -12 year experience in ASIC/DFT and various aspects simulation, Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug In depth knowledge and hands on experience in ATPG, coverage analysis, Transition delay test coverage analysis. In-depth knowledge and hands on experience in Silicon debug, yield optimization Expertise in test mode timing constraints definition, Hands on experience with prime time is an added advantage Expertise in scripting languages such as perl, shell, etc. is an added advantage Knowledge/experience in post Si debug support Experience in simulating test vectors Working experience in System Verilog, Vera, modelsim tools Ability to work in an international team, dynamic environment Ability to learn and adapt to new tools and methodologies. Ability to do multi-tasking work on several high priority designs in parallel. Past experience or ability to manage team Excellent problem solving skills Excellent communication and team work skills Experience with test tools such as Tetramax, Logic vision, Modelsim is highly desirable.

Role Description This is a full-time on-site role for DFT Engineer at Incise Infotech. DFT Engineer will be responsible for developing, implementing, and verifying the Design for testability (DFT) on complex system on chips (SOCs). The role also involves working with the physical design team to ensure the DFT requirements are met and with the verification team to ensure the DFT design is meeting the test coverage metrics. The ideal candidate will have experience in SOC level DFT techniques, ATPG, MBIST, JTAG, and boundary scan. Qualifications Bachelor's or Master's degree in Electrical/Electronics Engineering or equivalent 3+ years of experience in DFT domain Expertise in DFT methodologies - scan insertion, scan compression, boundary scan, and memory BIST Experience in DFT tools like Tessent, ATPG, MBIST, and JTAG Experience in the complete scan chain flow (ATPG, simulation, and test pattern generation) on complex SOCs Knowledge of STA, LEC, and physical design aspects related to DFT Experience in Shell/Perl/Tcl and other scripting languages Good communication skills and the ability to work well in a team environment Interested can share resume on Shubhanshi@incise.in

Experience: 5 + - Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPG generation & Simulations along with Pattern Porting/re-targeting and Coverage improvement -Experience with Scan, Compression, ATPG and simulations with Synopsys EDA tools. - Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. - Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. -Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process -Excellent problem solving and debugging skills. Proactive in nature - Excellent Customer interaction, Communication and Team work skills

Expert in implementing Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. In your new role you will: Responsible for SoC DFT Architecture definition / implementation / verification / silicon debug of SoC/Full Chip. Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. Responsible for ATPG, DRC analysis, Test coverage debug , Memory BIST implementation and verification. Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at / TDF / Bridging / Cell-aware / iddq fault models. Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations. Hands on experience in analysis and debug of above-mentioned test domains. Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out You are best equipped for this task if you have: ASIC flow understanding. Experienced in LEC, CLP, power analysis flow is preferred The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies . The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred Degree & Discipline: BE/B.Tech Electrical/Electronic or ME/M Tech in VLSI design. Experience in Industry: 12+ years of in DFT implementation, verification and post silicon debug areas

5years experience in VLSI EDA/CAD methodology development in areas of DFT, Scan/ATPG/MBIST. Good knowledge of the DFT domain specifically on Scan logic generation, insertion methodology. Exposure to using RTL, Netlist DRC tools like Synopsys Spyglass is preferable, Strong development skills in TCL, Python.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Primary responsibilities will include, Interface with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. MBIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting post silicon debug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 3-6 yrs of experience is preferred Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Like Requirements: 3 to 6 years of hands-on experience in DFT methodologies , with expertise in Scan & ATPG . Strong knowledge of DFT tools such as Synopsys, Mentor Graphics, or Cadence. Experience in fault modeling, pattern generation, and coverage analysis . Proficiency in scripting (TCL, Python, Perl, or Shell) for automation. Excellent problem-solving skills and ability to work in a fast-paced environment. Job Responsibilities: Implement and validate DFT architectures for complex SoCs. Perform scan insertion and ensure proper integration into the design. Develop and optimize ATPG patterns to achieve high fault coverage. Work closely with RTL, verification, and physical design teams to resolve DFT-related issues. Support post-silicon bring-up, debug, and ATE (Automated Test Equipment) testing.

Required Skills and Experience : Bachelors or Masters Degree or equivalent experience in Electronics Engineering, Microelectronics, Software Engineering or a related field. The role of Senior DFT engineer require 5+ years of industry experience with shown ability in DFT of highly sophisticated SOCs : Core skills include Scan Codec insertion, Memory BIST and Repair implementation, Logic BIST, ATPG, BSCAN & JTAG (IEEE1149.1 & IEEE1687), Fault Simulation, ATPG Fault models(SAF, TDF, SDD, PDT etc), SDF annotated gate level verification, Scan and Memory Diagnosis. Must have experience with Siemens, Synopsys and/or Cadence Cad tools. Shall have experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python. Responsibilities - Accountable for innovative DFT flow implementation(Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level. Help build flows that generate and validate ATPG patterns using simulations. Shall biuld flows that Validate the DFT implementation using RTL and Gate level simulation. Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation. Support the Silicon bring up activities to guarantee the highest stability of the test patterns/program. Chip in to the overall DFT methodology development. Nice to have Skills/Experience :- Shall have Knowledge of IEEE 1149.6, 1500 and 1838. Good experience on Hierarchical Scan implementations with core wrapping concepts Experience in handling multi-clock domains and low power design implementation. Knowledge/Experience on SSN, 2.5D or 3D IC DFT implementation. Communicate effusively with multi-functional functional teams in different geographies and time Zones. Time management and multi-tasking skills.

Mirafra Technologies Hiring DFT Lead Engineers: Experience - 7 to 12 years Notice Period - 0 to 90 days (45 days or lesser notice period will be preferred 1st) Location - Bangalore Please find the Job Description Below: Minimum 7+ years of relevant work experience in DFT. Good at Scan and ATPG. Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Fullchip level. Synopsys tools: DFT MAX, TetraMAX OR Cadence tools: RTL Compiler, Encounter Test OR Mentor Graphics tools: Tessent tool chain, TestKompress - Debussy, VCS/Questa/IUS - PT tool from Synopsys . Tool Experience - Cadence Modus / Synopsys DFTMax/TetraMax / Mentor/Tessent Expertise in coverage improvement techniques Experience in - Stuck at, Transition, Deley faults, Bridging fault, IDDQ ATPG simulation - with SDF - should possess good debug skills Scripting experience - TCL/Shell/Perl/Python Tester/ATE Pattern debug. if Interested, please share your updated resume at sayantikamajumdar@mirafra.com Thanks and Regards, Sayantika Majumdar Senior Talent Acquisition Specialist Mirafra Technologies Email - sayantikamajumdar@mirafra.com Call- +91 - 9007115796

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. o BE/BTech degree in CS/EE with 3+ years experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologies:JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. KEY RESPONSIBILITIES: Define and develop DFT feature verification requirements and test plans for current and next generation products Build comprehensive validation infrastructure including test bench components, agents, monitors, checkers, scoreboards Construct System Verilog and test sequences for comprehensive feature simulation, evaluate feature coverage and regression health Participate in methodology development to increase verification efficiency and effectiveness. PREFERRED EXPERIENCE: 8+ years of VLSI Design and DFT testability Deep understanding of VLSI DFx strategies (ex. JTAG, BIST, ATPG, Boundary Scan) Excellent scripting skills (ex. Perl, C shell, Python). Proficient in debugging RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Strong experience with Verilog, System Verilog, C, and C++ Working knowledge with EDA simulation tools including Synopsys VCS, Cadence NCSIM, Verdi Experience with UVM, OVM or equivalent Experience with formal verification techniques and industry tools Working knowledge of Unix/Linux OS and debug tools Strong analytical skills and attention to detail Excellent written and verbal communication Strong interpersonal skills and proven leadership Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary: Responsibilities Front-End/Digital design implementation of Sensor/Mixed signal digital blocks RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with SoC power management team for power sequencing requirements and system level considerations Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 8+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills. Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Engineering, Information Systems, or related field. 5+ years of Hardware Engineering or related work experience. About The Role :: Own and deliver scan insertion. Validate equivalence checks and Debug/resolve any DRC issues, Identify solutions and work with front-end team to ensure DFT DRCs are fixed. Analyzing and meeting ATPG coverage goals. Own and deliver MBIST insertion, validate Memory tests. Owns STA constraints and work with STA team to resolve timing violations. Mandatory Skills: Knowledge in MBIST Operations. Expertise in handling Mentor ATPG tools, Synopsys Synthesis & SMS tool sets. Experience in Test coverage analysis and Simulation of ATPG vectors & MBIST tests. Preferred Skills: Exposure to LBIST, Low Power design and Scripting. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field. 5-9 years Hardware Engineering experience or related work experience. like 1 Level of Responsibility: Works independently with minimal supervision. Decision-making may affect work beyond immediate work group. Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively. Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary: Responsibilities Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 6+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills. Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary responsibilities will include , Interfac e with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF) , transition fault (TDF ) models through the use of on-chip test compression techniques. M BIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBI ST verification using unit delay and min/max timing corner s imulations . Work with the P roduct /Test engineering teams on the delivery of manufacturi ng test patterns for ATE . Responsible for supporting post silicon debug effort, issue resolution . Responsible for Diagnostic Tool generation for ATPG , MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 1-6 year s experience in ASIC/DFT - simulation and Silicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement In depth knowledge and hands-on experience in ATPG - coverage analysis. In depth knowledge of Memory verification, repair and failure root-cause analysis. Experience with any of these tools is required ATPG - TestKompress MBIST - Mentor ETVerify Simulation - VCS (preferred), modelsim . Expertise in scripting languages such as Perl , shell, etc. is an added advantage Ability to work in an international team, dynamic environment with good communication skills Ability to learn and adapt to new tools , methodologies. Ability to do multi-tasking & work on several high priority designs in parallel Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.