562 Atpg Jobs - Page 10

Roles and Responsibility As per our discussion over call, please help us find some good candidate with minimum 5 or 6+ yrs of experience. Here is the job description we are looking for- Scan and ATPG for different fault models. Performing scan insertion, LEC checks, low power CLP checks IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests. Running zero delay and timing simulations and debugging on all the above aspects Contractor should be experienced and independent in debugging ATPG DRCs, coverage analysis and simulation debugs. Experience on automation and scripting would be helpful.

Our vision is to transform how the world uses information to enrich life for . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. What's Encouraged Daily: Completing various tasks in the netlist to GDSII implementation for partition(s), meeting schedule, and design goals. Collaborating with the Architect, Front End Design, and CAD teams to deliver best-in-class designs. Assisting Front End Design and Integration Engineers with SRAM/RF specification and synthesis design constraints. Resolving and improving design and flow issu...

ROLE & RESPONSIBILITIES: Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off. Be responsible for a comprehensive DFT plan. Incumbent to work with DFT and cross functional teams. To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field. ESSENTIAL SKILLS & EXPERIENCE: Strong fundamentals on DFT and ASIC cycle. Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player. Hands-on experience with DFT implementation using standard EDA and flow is a must. Experie...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFX - DFT The Role AECG SSD ASIC is a centralized ASIC design group within AMD’s ...

Bizoforce is actively hiring an experienced AI/ML Engineer to join our innovative team and work on cutting-edge solutions in Generative AI, LLMs, and multi-agent architectures This is a fully remote role based in India, ideal for professionals passionate about AI innovation and real-world deployment, Youll be contributing to advanced applications such as LLM-based tutoring systems, OCR-powered tools, AI content generators, and data-driven assistants in EdTech, enterprise, and healthcare domains A clinical background is a plus but not required, Key Responsibilities: Design, develop, and deploy scalable LLM-based systems, RAG pipelines, and Generative AI applications Engineer structured prompt...

| Location :Bangalore Note : These are fulltime roles and Notice can go from immediate -60 Days Max Job Descriptions for DFT: Required Technical and Professional Expertise in DFT Minimum 9 to 13 years of relevant experience. Proficient in DFT architectures & methodologies that includes Scan insertions, ATPG, MBIST, JTAG, etc. Sound knowledge of DFT tools/methodology from cadence /Synopsys/Mentor tools Good Experience in Python/Perl/TCL scriptingRole & responsibilities Preferred candidate profile

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Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation. Required Skills and Experience : This role is for a Senior Principal DFT Engineer with proven ability in Design for Test Experience coding Verilog RTL, TCL a...

Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation. Required Skills and Experience : This role is for a Principal DFT Engineer with proven ability in Design for Test Experience coding Verilog RTL, TCL and/or P...

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills VHDL,RTL coding,Mentor DfT tools,Caden...

Skill : DFT Lead/Manager with 5-15 Years Location : Bangalore/HYD Minimum 5 Years of Relevant DFT Experience Good Experience in Scan Insertion, Scan DRC Checks. Experience in Atpg,Mbist,Simulation,ijtag skills is MUST. Should have working knowledge in LBIST is Preferred. Good communication skills and Leadership skills. Able to manage client interactions and stake holder Management for regular status meetings. Please forward your updated profile to chakradhar.marupuru@quest-global.com below details Current CTC : Expected CTC: Notice Period :

ATE Test Engineer with experience in Teradyne- Ultraflex-RF Job Description In your new role you will: Develop and document Test plan for new IoT devices. Design and debug ATE Test Hardware and Software Production & Reliability. Debug new silicon on Automated Test Equipment. Bring quality and cost-effective Test solution for mass production. Oversee test related activities (HW & SW) with both internal and external Test house. Implement Test programs, modify and release into offsite production. Your Profile You are best equipped for this task if you have: Good understanding of semiconductor device fundamentals (Analog/Digital and Circuit Theory) Sound understanding of Semiconductor Design for...

Front End Director Location: Bangalore Front End Director Location: Bangalore Job Description: Our company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. We are a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics. Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Phys...

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Join...

ATE Senior Test Engineer Job Description In your new role you will: Develop and document Test plan for new MCU devices. Design and debug ATE Test Hardware and Software Production & Reliability. Debug new silicon on Automated Test Equipment. Bring quality and cost-effective Test solution for mass production. Oversee test related activities (HW & SW) with both internal and external Test house. Implement Test programs, modify and release into offsite production. Your Profile You are best equipped for this task if you have: Good understanding of semiconductor device fundamentals (Analog/Digital and Circuit Theory) Sound understanding of Semiconductor Design for Test (DFT) techniques such as ATPG...

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills. Mandatory Key Skills JTAG,ATPG DRC,LBIST,RTL coding,VHDL,DF...

You Are: You are a passionate and highly skilled engineer with deep expertise in Design-for-Test (DFT) RTL coding and pattern generation, backed by more than a decade of hands-on experience. You thrive in collaborative, cross-functional environments, working seamlessly with R&D teams, customers, and product managers to develop and deploy robust silicon lifecycle management solutions. Your technical proficiency spans DFT domain standards such as IEEE 1149.1, 1687/1500, SCAN, ATPG, and MBIST methodologies, and you bring a strong understanding of flow automation using TCL. You possess a keen analytical mind, enabling you to dissect micro-architecture, debug complex issues, and optimize test cov...

What You ll Be Doing: Providing expertise for test solutions during design planning, budgeting, and implementation. MBIST implementation and validation, including BIST architecture planning, memory grouping, pattern generation, validation, silicon bring-up, diagnostics analysis, and debug. Participating in customer s design and flow reviews. Driving, prototyping, and developing new Design for Test methodologies. Multitasking across various issues and priorities to help customers exploit new technologies. Collaborating with Solution Architects to develop and productize next-gen test technologies. The Impact You Will Have: Enhancing Synopsys ability to deliver cutting-edge test solutions that ...

Interfacewith design team to ensure DFT design rules andcoveragesare met. Generating high quality manufacturingATPGtest patterns for stuck-at(SAF), transition fault(TDF)modelsthrough the use ofon-chip test compression techniques. MBISTverification(including repair),testpattern generation through Mentor tool. ATPG(SAF, TDF)and MBISTverification usingunit delay and min/maxtiming cornersimulations. Workwith the Product/Testengineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting postsilicondebug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG,MBISTand bring-up on ATE. Developing,enhancingandmaintainingscripts as necessary...

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in g...

We are looking for a skilled DFT Engineer with 3 to 7 years of experience to join our team in the IT Services & Consulting industry. The ideal candidate will have a strong background in designing and implementing fault detection and testing strategies. Roles and Responsibility Design and develop test plans, test cases, and test scripts for complex systems. Collaborate with cross-functional teams to identify and prioritize testing requirements. Develop and maintain automated testing frameworks and tools. Analyze test results, identify defects, and work with development teams to resolve issues. Participate in agile development methodologies and contribute to process improvements. Stay up-to-da...

Skills/Experience: Proficient in Scan, specializing in ATPG and Pattern verification at Block and Full chip level. Skilled in Scan insertion, ATPG, DRC analysis, Low Coverage Analysis, JTAG and IJTAG. Experienced in scripting for flow automation, using Siemens tools (Tessent), Synopsys tools (DFTMAX, Tetra MAX, VCS, DFT Compiler), Verdi. Familiar with tools: NC-SIM/Irun, Sim-Vision, XCELIUM. Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC ver...

Good understanding on DFT concepts like SCAN/ATPG/BSCAN/MBIST. Experience in Mbist insertion using tessent and mbist validation Experience in ATPG, drc fix and coverage analysis. Experience in scan synthesis. Hands on experience on Simulations with and without timing. Post silicon debug support. Bachelors or Masters degree in Electrical Engineering or related field No. of Vacancies Responsible For Roles & Responsibilities: Good understanding on DFT concepts like SCAN/ATPG/BSCAN/MBIST. Experience in Mbist insertion using tessent and mbist validation Experience in ATPG, drc fix and coverage analysis. Experience in scan synthesis. Hands on experience on Simulations with and without timing. Post...

Mirafra Technologies Hiring DFT Engineers: Experience - 5 to 10 years Notice Period - 0 to 90 days (30 days or lesser notice period will be preferred 1st) Location - Bangalore Please find the Job Description Below: 5+ years of relevant work experience in DFT. Good at Scan and ATPG. Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Fullchip level. Synopsys tools: DFT MAX, TetraMAX OR Cadence tools: RTL Compiler, Encounter Test OR Mentor Graphics tools: Tessent tool chain, TestKompress - Debussy, VCS/Questa/IUS - PT tool from Synopsys . Tool Experience - Cadence Modus / Synopsys DFTMax/TetraMax / Mentor/Tessent Ex...