- Experience with EDA tools associated to Analog IC design - Analog circuit design and simulations - new design/technology porting flows - Participate in the new design/technology porting - Engage with the PDK and Device teams Provident fund Health insurance
3-5 Years experience in DFT Experience with IJTAG is a must. Hands-on experience in scan insertion, ATPG DRC, and coverage analysis Please do share your updated resume to - dft@greensemis.com Accessible workspace Flexi working Health insurance
Understanding of electrical circuit analysis, design, and test fundamentals Automation of Analog Characterization Setups Bring up of Silicon & Analog Validation Platforms like Analog Board for new ASIC/SoC design. • Knowledge of C is must Health insurance Provident fund
Role & responsibilities STA engineer, for multinational company Preferred candidate profile • Block level Timing Constraints enablement & analysis ; • Clocking & Data flow understanding ; • Well versed in reviewing check_timing and Constraints QoR checks + Constraints Validation understanding ; • Able to interact with Implementation team counterparts for block timing closure ; • CTS building understanding along with Clock Tree spec review/closure ; • Timing ECOs & Final Timing last mile closure at block level ; • Scripting like TCL, Unix etc min 2.6 years of relevant experience is a must Immediate joiners highly preferred