169 Atpg Jobs - Page 5

Role Description This is a full-time on-site role for DFT Engineer at Incise Infotech Pvt. Ltd. DFT Engineer will be responsible for developing, implementing, and verifying the Design for testability (DFT) on complex system on chips (SOCs). The role also involves working with the physical design team to ensure the DFT requirements are met and with the verification team to ensure the DFT design is meeting the test coverage metrics. The ideal candidate will have experience in SOC level DFT techniques, ATPG, MBIST, JTAG, and boundary scan. Qualifications Bachelor's or Master's degree in Electrical/Electronics Engineering or equivalent 3+ years of experience in DFT domain Expertise in DFT methodologies - scan insertion, scan compression, boundary scan, and memory BIST Experience in DFT tools like Tessent, ATPG, MBIST, and JTAG Experience in the complete scan chain flow (ATPG, simulation, and test pattern generation) on complex SOCs Knowledge of STA, LEC, and physical design aspects related to DFT Experience in Shell/Perl/Tcl and other scripting languages Good communication skills and the ability to work well in a team environment Interested can share resume on Shubhanshi@incise.in

Job Description: We are looking for a skilled DFT Engineer with 13 years of experience in ASIC/SoC test design. The ideal candidate will work on scan insertion, ATPG, MBIST/LBIST, and DFT verification using industry-standard tools. Key Skills: DFT implementation: Scan, MBIST, LBIST, Boundary Scan Tools: Tessent, DFT Compiler, Tetramax, Modus Scripting: Python, Perl, Tcl Good understanding of STA and RTL flows Strong debugging & communication skills.

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Automatic Test Pattern Generation (ATPG) Good to have skills : NA Minimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities: Expected to be an SME Collaborate and manage the team to perform Responsible for team decisions Engage with multiple teams and contribute on key decisions Provide solutions to problems for their immediate team and across multiple teams Lead the application design and development process Coordinate with stakeholders to gather requirements Ensure project milestones are met Professional & Technical Skills: Must To Have Skills:Proficiency in Automatic Test Pattern Generation (ATPG) Strong understanding of software development lifecycle Experience in application architecture design Knowledge of database management systems Hands-on experience in application testing Additional Information: The candidate should have a minimum of 7.5 years of experience in Automatic Test Pattern Generation (ATPG) This position is based at our Bengaluru office A 15 years full-time education is required Qualifications 15 years full time education

Develop and implement high-performance, low-power, area-efficientdigital designs for ASICs and SoCs using industry-standard EDA tools. Work closely with design teams to understand the requirements andconstraints of the design, and provide feedback on design feasibility,timing and power. Write and implement block level and top-levelconstraints for synthesis, perform timing closure and power analysis.Debug and resolve design issues related to synthesis, timing, power, andarea. Understanding of DFT flows, including scan insertion and ATPG.Optimize designs for power, performance, and area, and meet design goalswithin the given schedule. Implement pipelining at different levels forperformance optimization and timing closure. Perform power analysis andoptimize designs for low power. Proficient with EDA tools fromSynopsys/Cadence/Mentor. Excellent analytical & communication skills.Shown ability to collaborate in a multi-functional environment,cross-site or cross-time zone. Proficient in Tcl and Perl or otherscripting relevant language is a plus Your Profile Bachelors or Masters in Electrical/Electronics Engineering with 5+ yearsof relevant experience. In-depth knowledge of synthesis methodologies and tools from leading EDAvendors. Experience with writing design constraints for synthesis, timing closureand pipelining at different levels for performance optimization andtiming closure. Experience with power analysis and optimization flows such as powergating, clock gating, voltage scaling, and dynamic voltage frequencyscaling. Experience with scripting languages such as Perl, Python, or Tcl . Excellent problem-solving skills and ability to work independently andin a team environment. Strong communication and interpersonal skills, with the ability to interact effectively with cross-functional teams. Proven track record of delivering successful designs on time and meeting performance, power, and area goals.

Required Skills: The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills."

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years"™ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division) s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers. The candidate should have in-depth knowledge of DFT concepts and should be well experienced in various aspects of DFT -ATPG, MBIST & JTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage. Experience with either Mentor Graphics DFT tools (TestKompress, Fastscan) or Synopsys DFT tools (DFTMax, Tetramax) is highly desirable. The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently and also supervise the work of other team members as required. The candidate should possess excellent communication skills. Educational qualification & Experience Level : Bachelor s degree with 8+ years of relevant experience or Master s degree with 6+ years of relevant experience Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary: ResponsibilitiesFront-End/Digital design implementation of Sensor/Mixed signal digital blocks RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules.Work with SoC power management team for power sequencing requirements and system level considerationsWork with functional verification team on test-plan development and debug.Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA.UPF writing, power aware equivalence checks and low power checks.DFT insertion and ATPG analysis for optimal SAF, TDF coverage.Provide support to SoC integration and chip level pre/post-silicon debug. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. Skills & ExperienceMTech/BTech in EE/CS with hardware engineering experience of 8+ years.Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA.Experience with post-silicon bring-up and debug is a plus.Able to work with teams across the globe and possess good communication skills. Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3068889

• Should have worked hands-on extensively on full chip DFT design, • implementation, vector generation/verification, JTAG, Boundary scan & Simulation. • Experience with Scan, Compression, ATPG & Simulations with Mentor/Synopsys/ Cadence tools. Required Candidate profile • Participated in Successful Tapeouts of SoC/ASIC chips at 14nm or below. • Develop/Automate flows & scripts in Perl/Tcl to enhance the DFT methodologies & process. • Logic BIST knowledge is a plus.

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division) s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics It involves working with the Physical Design & STA team for DFT mode timing closure The role could also involve direct interaction with external customers The candidate should have in-depth knowledge of DFT concepts and should be well experienced in various aspects of DFT -ATPG, MBIST & JTAG The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug Strong problem solving & debugging skills are a must Expertise in scripting languages such as perl, shell, etc is an added advantage Experience with either Mentor Graphics DFT tools (TestKompress, Fastscan) or Synopsys DFT tools (DFTMax, Tetramax) is highly desirable The candidate should have worked with team across multiple geographies The candidate should be able to handle his/her work independently and also supervise the work of other team members as required The candidate should possess excellent communication skills Educational qualification & Experience Level : Bachelor s degree with 8+ years of relevant experience or Master s degree with 6+ years of relevant experience

We are seeking innovative and out-of-the-box thinking Design For Test (DFT) Engineers to be a part of the Fast Solution Team under the Test Group at Synopsys. You are someone who thrives in a project-oriented environment, delivering comprehensive DFT solutions ranging from integration to silicon bring-up for customers designing digital ICs of varying complexity. You excel in assessing customer methodologies and flows, gathering requirements, and proposing solutions. You are adept at providing technical support to ensure customer success and satisfaction, winning new customers through product demonstrations, evaluations, and competitive benchmarking. You are skilled in resolving technical problems, training, and account management, and you can interact effectively with end-users at customer sites and with first-level managers. You are also responsible for working with Solution Architects to develop and productize the next-gen test technologies. Your role involves prototyping new methodologies, analyzing gathered data, identifying the viability of technology, and presenting the findings under the guidance of a Solution Architect. What You ll Be Doing: Providing expertise for test solutions during design planning, budgeting, and implementation. MBIST implementation and validation, including BIST architecture planning, memory grouping, pattern generation, validation, silicon bring-up, diagnostics analysis, and debug. Participating in customer s design and flow reviews. Driving, prototyping, and developing new Design for Test methodologies. Multitasking across various issues and priorities to help customers exploit new technologies. Collaborating with Solution Architects to develop and productize next-gen test technologies. The Impact You Will Have: Enhancing Synopsys ability to deliver cutting-edge test solutions that meet customer needs. Contributing to the successful integration and silicon bring-up of complex digital ICs. Ensuring high customer satisfaction through effective technical support and problem resolution. Driving innovation in test methodologies and technologies. Supporting the development of next-gen test technologies that push the boundaries of whats possible. Playing a key role in winning new customers and expanding Synopsys market presence. What You ll Need: Minimum BS+10 years of relevant experience/MS+8 years of relevant experience in Electrical Engineering, Computer Engineering, or other relevant fields of study. Experience with RTL coding, DFT insertion, ATPG, MBIST architecture planning, insertion, validation, pattern generation, and silicon bring-up. Excellent knowledge of memory BIST flows, memory fault models, MBIST algorithms, hard/soft repair, and eFuse repair flow. Experience in handling memory BIST for large, complex SoCs with various IPs. Exposure to MBIST of automotive designs is a plus. Good understanding of protocols like 1149.1, 1500, 1687.

Implementing DDR and HBM PHYs for customer ASICs and SOCs in the DDR and HBM PHY Hardening service line. Performing synthesis, physical design, verification, design for test, and ATPG. Contributing as a senior member of a design team or as a project design engineer working with both internal and external design teams. Providing regular updates to the manager on project status. Representing the organization on business unit and/or company-wide projects. Guiding more junior peers with aspects of their job and frequently networking with senior internal and external personnel in your area of expertise. The Impact You Will Have: Enhancing the reliability and performance of DDR and HBM PHYs for customer ASICs and SOCs. Contributing to the success of complex projects through innovative problem-solving and technical expertise. Ensuring timely delivery of high-quality design solutions to our customers. Improving the efficiency and effectiveness of the design process through your autonomous judgment and technical knowledge. Strengthening Synopsys position as a leader in chip design and verification through your contributions. Mentoring and guiding junior team members, fostering a collaborative and innovative team environment. What You ll Need: A minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in state-of-the-art CAD tools such as DC, PT, ICC2/FC, and ICV. Experience with advanced technologies like FinFet. Strong problem-solving skills and the ability to autonomously resolve a wide range of issues. Excellent verbal and written communication skills. Who You Are: An innovative thinker with a passion for technology and continuous learning. A collaborative team player who excels in a dynamic and fast-paced environment. A mentor and guide for junior team members. A strong communicator with the ability to network effectively with senior personnel. A composed and reliable professional who can handle risks and uncertainty with ease.

We are looking for a Fellow-level Engineer to join our team to develop world-class DFT architecture for EPYC Server products. In this role you will be engaged with the SoC Architects, Micro Architects, PD Engineers, Product Engineers, etc, to define and implement the DFT Architecture, guide/technically lead the DFT Team to ensure right pre-si verification is done for the DFT logic, and the highest level of Scan coverage is achieved to hit the product goals. You will also be responsible for driving innovation to continuously improve the execution and also drive TTR (Test Time Reduction) THE PERSON: You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities. KEY RESPONSIBILITIES: Work closely with the SoC Architecture and uArch teams to define the DFT architecture. Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean silicon bring-up Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to comprehend and validate all the usage models Work with the post-silicon team on debug support and to help root-cause any failures Be upto date with the industry trends and bring-in the latest to the AMD products Work with DFT Tool Vendors and drive improvements based on our requirements REQUIREMENTS: 15+ years of in-depth DFT experience having driven multiple Tapeouts and silicon bring-ups across different process nodes. Good understanding and exposure to SoC design and architecture Very good understanding of verif and timing concepts having handled DFT timing closure Exposure to all DFT concepts such as JTAG, SCAN, MBIST, BScan, etc Comfortable with VCS/Verdi and Mentor TK. Logical in thinking and ability to gel we'll within a team Good stakeholder management Ability to quickly adapt to changes and handle pressure Good communication and leadership skills ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer engineering/Electrical Engineering

ROLE & RESPONSIBILITIES: Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off. Be responsible for a comprehensive DFT plan. Incumbent to work with DFT and cross functional teams. To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field. ESSENTIAL SKILLS & EXPERIENCE: Strong fundamentals on DFT and ASIC cycle. Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player. Hands-on experience with DFT implementation using standard EDA and flow is a must. Experience on latest technology (28nm,16nm,7 nm) EDUCATION BACKGROUND: B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.

The candidate should have skills and 5+ yrs in the field of scan and ATPG DFT knowledge with hands on experience. Scan extraction and DRC analysis along with Coverage debugs. ATPG experience and have to work on setup creation/pattern generations and debugs. Hands on Simulation experience with and without Timing. Post silicon debug support and scripting knowledge for day-to-day executions. I have to analyses the issues and need to react quickly with the team player's be a good Team player.

We make real what matters. This is your role. At Aprisa, we offer complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Our detail-route-centric architecture and hierarchical database enable you to accelerate design closure and achieve optimal quality of results at a driven runtime. We're excited to be working on the next-generation RTL-to-GDSII solution, and we want YOU to be a part of this innovative journey! This is the Role Drive and be responsible for the design and development of various pieces of the RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. Guide and lead others toward successful project completion by innovating and implementing powerful solutions. Collaborate with a hardworking team of experts. Must-Have Requirements B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college with 5-8 years of experience in software development. Validated understanding of C/C++, algorithms, and data structures. Demonstrate excellent problem-solving and analytical skills. Lead and encourage the team with your expertise. Great to Have Experience in: You will have the opportunity to develop RTL synthesis tools and work with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Additionally, you will design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly valued, as well as your proficiency in using scripting languages like Python and Tcl.

Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IP SoC handoff. Key Responsibilities: Design and develop cache architectures, including L1, L2, and L3 caches. Optimize cache performance, power, and area through innovative design techniques. Work closely with backend (BE) engineers to achieve timing closure and resolve any issues. Conduct static timing analysis (STA) and optimize the design for timing. Utilize lint, CDC (Clock Domain Crossing), and other design tools to ensure design quality and robustness. Implement and adhere to best practices in RTL design Collaborate with microarchitecture, RTL, verification, and physical design teams to ensure seamless integration of cache subsystems. Document design specifications, implementation details, and verification results. Participate in design reviews and provide feedback on other team members' designs. Qualifications Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field. 5-15 years of proven experience in design and micro-architecture. Strong understanding of memory hierarchy, cache coherence, and performance optimization techniques. Proficiency in hardware description languages (HDL) such as Verilog or VHDL. Experience integrating BIST and DFT features into RTL designs. Experience implementing Error Correction Code (ECC) mechanisms in cache designs. Knowledge of error detection, correction, and recovery techniques. Experience with simulation and verification tools (e.g., ModelSim, VCS). Experience using lint, CDC, and other design tools to ensure design quality. Proficiency in static timing analysis (STA) and timing closure techniques. Familiarity with physical design constraints and considerations. Excellent problem-solving skills and attention to detail. Strong communication and teamwork abilities.

We are looking for a talented Member of Technical Staff (MTS) with expertise in SoC Scan, Automatic Test Pattern Generation (ATPG), pattern retargeting, and simulations. The ideal candidate will play a crucial role in developing and verifying robust DFT solutions to ensure the quality and testability of our cutting-edge SoC designs. Key Responsibilities: Develop and execute SoC Scan insertion strategies and ensure integration across various modules. Generate and validate ATPG patterns to achieve high fault coverage for SoC designs. Perform pattern retargeting and conduct thorough simulations to ensure test reliability and efficiency. Debug and resolve test coverage gaps or failures during pattern simulations and silicon testing. Collaborate with cross-functional teams to ensure seamless DFT implementation and validation processes. Optimize test methodologies to improve yield and reduce test time. Required Skills: Strong hands-on experience in SoC Scan implementation and ATPG pattern generation. Proficiency in pattern retargeting and running simulations to ensure high-quality results. Familiarity with industry-standard DFT tools like Mentor Tessent, Synopsys TetraMAX, or Cadence Modus. Solid understanding of RTL design, verification, and debugging. Expertise in scripting languages (e.g., Python, TCL, Perl) for test process automation. Problem-solving skills for silicon debug and test failure analysis. Preferred Qualifications: Experience with low-power ATPG techniques and fault diagnostics. Knowledge of advanced DFT features such as compression and hierarchical ATPG. Exposure to post-silicon validation and production test flows. Education: Bachelors/Masters degree in Electrical/Electronics Engineering, Computer Engineering, or related field.

The candidate must have thorough knowledge of DFT basics such as DFT RTL insertion. scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture Proficient in logic design using Verilog Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

Job Title: Member of Technical Staff (MTS) DFT Verification Experience: 6+ years Location: Bangalore Job Description: We are seeking a dedicated and experienced Member of Technical Staff (MTS) specializing in DFT Insertion and Verification . The candidate will play a key role in ensuring the robustness and reliability of Tile and SoC designs by implementing and verifying advanced test architectures. Key Responsibilities: Perform SMS (Structural Mode Scan) Insertion and verification at both Tile and SoC levels. Design and verify Memory BIST (Built-In Self-Test) architectures, including initialization and integration. Implement and validate memory repair strategies, including fuse programming (eFuse) and redundancy management. Debug and optimize DFT flows to meet high fault coverage and manufacturability standards. Collaborate with cross-functional teams to ensure seamless DFT integration across various design phases. Analyze test results, resolve silicon and test-related issues, and contribute to yield improvements. Required Skills: Expertise in SMS Insertion and verification for Tile and SoC level designs. Proficiency in Memory BIST architecture, including repair mechanisms and eFuse configuration. Hands-on experience with DFT tools like Mentor Tessent, Synopsys DFT Compiler, or Cadence Modus. Strong scripting skills in Python, Perl, or TCL for automation of test flows. Knowledge of RTL design and debugging (Verilog/VHDL). Excellent problem-solving and analytical skills, especially in debugging silicon failures. Preferred Qualifications: Experience with low-power DFT methodologies and advanced compression techniques. Familiarity with industry standards for JTAG and boundary scan. Hands-on experience with post-silicon validation, bring-up, and characterization.

Skills / Experience: Proficient in Scan, specializing in ATPG and Pattern verification at Block and Full chip level. Skilled in Scan insertion, ATPG, DRC analysis, Low Coverage Analysis, JTAG and IJTAG. Experienced in scripting for flow automation, using Siemens tools (Tessent), Synopsys tools (DFTMAX, Tetra MAX, VCS, DFT Compiler), Verdi. Familiar with tools: NC-SIM/Irun, Sim-Vision, XCELIUM. Education Qualification: BTECH/ MTECH in Electrical/ Electronics/ Computer Science Engineering or Equivalent.

About The Role Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Hands on experience in IP RTL, Microarchitecture, TFM, synthesis, cdc, lint, spyglass, rdc. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc) Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 8-14 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited toSystem Verilog, Python/Perl/Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools and flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

About The Role The Graphics hardware IP team , within the CGAI Client Compute Group and AI, is responsible for design and development of Graphics, Media and Display IPs as well as discrete Graphics SoCs GPUs, targeting both Client Device and Datacenter markets. The XSE organization is at the center of Intel's push into the discrete Graphics SoCs ARC GPUs market segment targeting next-generation applications such as High-performance computing, Deep learning / training, Cloud Graphics, Media analytics, High-end gaming. Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration of the GPU block. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Experience listed below would be obtained through relevant schoolwork, internships, jobs and/or research experience. Minimum skills and Experience: Bachelors in Electrical/Computer Engineering or related field with 9+ years of academic or industry experience. Or a Masters in the same fields with 8+ Years of academic or industry experience. Your experience should be in the following: Experience across all the DFT features such as TAP/JTAG, SSN, Scan/ATPG or Array DFT (MBIST/PBIST), Silicon bring-up, DFT micro-architecture. SoC IP DFT design integration or verification. EDA tools such as ATPG tools, Mentor Tessent shell, VCS simulation and/or debug tools, Synopsys tool. Silicon enabling debug or test pattern development experience Structural design flows, including timing, routing, placement or clocking analysis SOC architecture, RTL coding and post silicon debug. Experience in handling DFT timings constraints. Additionally: RTL insertion and integration will be a plus. Knowledge of UVM and OVM will be added advantage. Knowledge of system verilog is must. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.