169 Atpg Jobs - Page 3

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary Responsibilities Will Include, ▪ Interface with design team to ensure DFT design rules and coverages are met. ▪ Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. ▪ MBIST verification (including repair), test pattern generation through Mentor tool. ▪ ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. ▪ Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. ▪ Responsible for supporting post silicon debug effort, issue resolution. ▪ Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. ▪ Developing, enhancing and maintaining scripts as necessary Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Of 2-6 Years’ Experience In ASIC/DFT – simulation and Silicon validation ▪ Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement ▪ In depth knowledge and hands-on experience in ATPG - coverage analysis. ▪ In depth knowledge of Memory verification, repair and failure root-cause analysis. ▪ Experience With Any Of These Tools Is Required ▪ ATPG - TestKompress ▪ MBIST - Mentor ETVerify ▪ Simulation - VCS (preferred), modelsim. ▪ Expertise in scripting languages such as Perl, shell, etc. is an added advantage ▪ Ability to work in an international team, dynamic environment with good communication skills ▪ Ability to learn and adapt to new tools, methodologies. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3070714 Show more Show less

Expert in implementing Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. In your new role you will: Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip. Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification. Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at/TDF/Bridging/Cell-aware/iddq fault models. Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations. Hands on experience in analysis and debug of above-mentioned test domains. Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out You are best equipped for this task if you have: ASIC flow understanding. Experienced in LEC, CLP, power analysis flow is preferred The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred Degree & Discipline: BE/B.Tech Electrical/Electronic or ME/M Tech in VLSI design. Experience in Industry: 12+ years of in DFT implementation, verification and post silicon debug areas. #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

Job Details The Candidate will be involved in all aspects of DFT with prime focus on selected Deliverables. He/She will get exposure to SoC level DFT practices and Post-Silicon Debugs. The Team is responsible for delivering Ultra Low Power MCUs that will cater to today's IOT & Edge Processing Needs with applications varying from industrial to consumer wearable devices. Requirements BTech/ MTech with minimum 2years of Relevant Experience. Strong DFT Concepts with HandsON experience on DFT Tools & Methodologies. Experience on ATPG, Scan Insertion, DFT-DRCs, GLS, is preferred. Perl/TCL Scripting. Strong Analytical & Problem Solving Skills MBIST/LBIST is a plus More information about NXP in India... Show more Show less

Alternate Job Titles: DFT Solutions Engineer Design for Test Engineer DFT Project Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced Solutions Engineer with a proven track record in project execution and overall project management within the semiconductor industry. You excel in deploying Synopsys DFT technologies on customer designs, ensuring projects are completed on schedule and with high quality. You are adept at managing multiple projects simultaneously, recognizing and mitigating risks, and working proactively on contingency plans. You possess exceptional verbal and written communication skills, leadership abilities, and a strong teamwork ethic. Your proficiency in PowerPoint, Excel, and Word, along with your ability to work unsupervised, makes you a valuable asset to any team. You have a solid background in the implementation of DFT technologies and are eager to work cross-functionally with internal teams, gaining exposure and visibility on a global scale throughout the organization. What You’ll Be Doing: Deploying Synopsys DFT technologies on key customers’ designs and successfully executing the project. Acting as the focal point of contact and managing all external and internal communications across cross-functional teams. Planning and directing project schedules, identifying and escalating issues, and driving problems to resolution. Identifying and managing risks, ensuring the completion of projects on schedule and with high quality. Organizing interdepartmental activities and ensuring clear and concise communication. Working closely with internal teams (Applications Engineering, R&D) to meet customer requirements and achieve goals and targets. The Impact You Will Have: Ensure successful deployment of Synopsys DFT technologies on customer designs. Facilitate effective communication and coordination between cross-functional teams. Drive projects to completion, meeting deadlines and maintaining high standards of quality. Identify and mitigate risks to ensure project success. Contribute to the overall success of Synopsys by delivering high-quality solutions that meet customer needs. Enhance customer satisfaction and build strong, long-lasting relationships with key customers. What You’ll Need: Solid background and proven track record in the implementation of DFT technologies. Experience in deploying Scan Compression, On-chip DFT Fabric, ATPG, Diagnosis, MemoryBIST, LogicBIST, and Boundary Scan. Proficiency in project management and the ability to manage multiple projects simultaneously. Exceptional verbal/written communication, leadership, interpersonal, and teamwork skills. Good working knowledge of PowerPoint, Excel, and Word. Who You Are: A detail-oriented and process-driven professional with a strong engineering background. You possess excellent organizational skills and the ability to communicate effectively across various levels of the organization. You are a proactive problem-solver who can work independently and within a team. Your leadership abilities and teamwork ethic enable you to drive projects to successful completion, ensuring high-quality outcomes and customer satisfaction. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team that focuses on deploying Synopsys DFT technologies to key customer designs. This team works cross-functionally with internal teams such as Applications Engineering and R&D, and has a global presence within the organization. Together, you will strive to meet customer requirements and achieve project goals, contributing to the overall success of Synopsys. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

DFT Lead / Manager Location: Bangalore Description Our main business focuses on automotive microcontrollers and SoCs. The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips. we will continue to integrate the latest electronic and electrical architecture (E/EA) designs from automakers, realize the demands of the next-generation software-defined vehicle, and apply a chip design-oriented, human-centric service-oriented architecture (SOA) to the automotive field. This approach aims to meet the diverse neaeds of users and provide consumers with a new user experience. Job Location: Bangalore We are seeking a skilled Design for Test (DFT) Architect/Lead/Manager to join our team. This role is pivotal in ensuring the testability and manufacturability of our ASIC/SoC products designed for the automotive industry. The ideal candidate will have extensive experience in DFT methodologies and will lead a team of engineers to develop robust test strategies that meet industry standards. Key Responsibilities: DFT Strategy Development: Design and implement DFT methodologies for ASIC/SoC products, focusing on automotive applications to ensure high quality and reliability. Architecture Design: Collaborate with hardware and software teams to integrate DFT features into the product architecture, ensuring compatibility with automotive testing standards. Team Leadership: Lead a team of DFT engineers, providing mentorship and technical guidance to enhance their skills and capabilities. Test Planning: Develop comprehensive test plans, including ATPG, BIST, and scan insertion strategies, to optimize fault coverage and reduce test costs. Collaboration: Work closely with design, validation, and manufacturing teams to align DFT strategies with overall product goals and requirements. Quality Assurance: Establish metrics and benchmarks for DFT processes, and ensure compliance with automotive industry standards (e.g., ISO 26262). Tool Development: Evaluate and implement DFT tools and methodologies to improve test efficiency and effectiveness. Continuous Improvement: Stay updated with industry trends and technologies in DFT and automotive testing, driving innovation within the team. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in DFT for ASIC/SoC design, with a strong background in automotive applications. Proven experience leading DFT teams and managing complex projects. In-depth knowledge of DFT techniques such as scan design, boundary scan, BIST, and fault simulation. Familiarity with automotive industry standards and regulations (e.g., ISO 26262). Proficiency in using DFT tools and EDA software. Strong problem-solving skills and ability to work collaboratively in a fast-paced environment. Excellent communication skills, both verbal and written. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

DFT Lead / Manager Location: Bangalore Description Our main business focuses on automotive microcontrollers and SoCs. The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips. we will continue to integrate the latest electronic and electrical architecture (E/EA) designs from automakers, realize the demands of the next-generation software-defined vehicle, and apply a chip design-oriented, human-centric service-oriented architecture (SOA) to the automotive field. This approach aims to meet the diverse neaeds of users and provide consumers with a new user experience. Job Location: Bangalore We are seeking a skilled Design for Test (DFT) Architect/Lead/Manager to join our team. This role is pivotal in ensuring the testability and manufacturability of our ASIC/SoC products designed for the automotive industry. The ideal candidate will have extensive experience in DFT methodologies and will lead a team of engineers to develop robust test strategies that meet industry standards. Key Responsibilities: DFT Strategy Development: Design and implement DFT methodologies for ASIC/SoC products, focusing on automotive applications to ensure high quality and reliability. Architecture Design: Collaborate with hardware and software teams to integrate DFT features into the product architecture, ensuring compatibility with automotive testing standards. Team Leadership: Lead a team of DFT engineers, providing mentorship and technical guidance to enhance their skills and capabilities. Test Planning: Develop comprehensive test plans, including ATPG, BIST, and scan insertion strategies, to optimize fault coverage and reduce test costs. Collaboration: Work closely with design, validation, and manufacturing teams to align DFT strategies with overall product goals and requirements. Quality Assurance: Establish metrics and benchmarks for DFT processes, and ensure compliance with automotive industry standards (e.g., ISO 26262). Tool Development: Evaluate and implement DFT tools and methodologies to improve test efficiency and effectiveness. Continuous Improvement: Stay updated with industry trends and technologies in DFT and automotive testing, driving innovation within the team. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in DFT for ASIC/SoC design, with a strong background in automotive applications. Proven experience leading DFT teams and managing complex projects. In-depth knowledge of DFT techniques such as scan design, boundary scan, BIST, and fault simulation. Familiarity with automotive industry standards and regulations (e.g., ISO 26262). Proficiency in using DFT tools and EDA software. Strong problem-solving skills and ability to work collaboratively in a fast-paced environment. Excellent communication skills, both verbal and written. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years’ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG In depth knowledge of DFT concepts. In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. Expertise in scripting languages such as perl, shell, etc. Experience in simulating test vectors. Knowledge of equivalence check and RTL lint tool (like spyglass). Ability to work in an international team, dynamic environment Ability to learn and adapt to new tools and methodologies. Ability to do multi-tasking & work on several high priority designs in parallel. Excellent problem-solving skills Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. 3 years of experience with multiple SoCs with Silicon success. Experience with chip design flow. Preferred qualifications: Experience in micro-architecture and coding in one or more of the following areas: memory compression, interconnects, coherence, cache. Knowledge of ARM based SoC, Debug (coresight). Understanding of cross-domain involving domain validation, design for testing, physical design, and software. Understanding of Verilog or System Verilog language. Proficiency with ASIC design methodologies for front quality checks like; Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Responsibilities Work on both the IP design and integration activities including: plan tasks, support, hold code and design reviews, contribute on sub-system/chip-level integration. Interact closely with the architecture team and develop implementation strategies to meet quality, schedule, and power performance area for IPs. Interact with the subsystem team and plan System-on-Chip (SoC) milestones, plan quality checks as part of SoC milestones (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.). Work with cross-functional teams of verification, design for test, physical design, emulation, and software to make design decisions and represent project status throughout the development process. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form . Show more Show less

Role & responsibilities DFT Engineer Must-Have: •Tools: Synopsys DFT Compiler, Tessent, Mentor TestKompress, Tetramax, Fastscan •Techniques: •Scan Insertion (ATPG) •Boundary Scan (JTAG) •MBIST, LBIST •Compression techniques •Stuck-at, Transition fault models •Simulation and validation of test vectors •DFT signoff and coverage reports •STA constraint generation for test modes Nice-to-Haves: •Tapeout experience •Knowledge of low-power test techniques •Integration of DFT at SoC level Common Green Flags Across Roles: •Product or IP ownership •Clear mention of project responsibilities (not just team contribution) •Mention of tapeouts or silicon-proven designs •Stable employment history (avoiding frequent jumps unless justified) •Notice period 90 days •Clarity in resume: tools, technology nodes, project domains

Deploying Synopsys DFT technologies on key customers designs and successfully executing the project. Acting as the focal point of contact and managing all external and internal communications across cross-functional teams. Planning and directing project schedules, identifying and escalating issues, and driving problems to resolution. Identifying and managing risks, ensuring the completion of projects on schedule and with high quality. Organizing interdepartmental activities and ensuring clear and concise communication. Working closely with internal teams (Applications Engineering, R&D) to meet customer requirements and achieve goals and targets. The Impact You Will Have: Ensure successful deployment of Synopsys DFT technologies on customer designs. Facilitate effective communication and coordination between cross-functional teams. Drive projects to completion, meeting deadlines and maintaining high standards of quality. Identify and mitigate risks to ensure project success. Contribute to the overall success of Synopsys by delivering high-quality solutions that meet customer needs. Enhance customer satisfaction and build strong, long-lasting relationships with key customers. What You'll Need: Solid background and proven track record in the implementation of DFT technologies. Experience in deploying Scan Compression, On-chip DFT Fabric, ATPG, Diagnosis, MemoryBIST, LogicBIST, and Boundary Scan. Proficiency in project management and the ability to manage multiple projects simultaneously. Exceptional verbal/written communication, leadership, interpersonal, and teamwork skills. Good working knowledge of PowerPoint, Excel, and Word.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary: Responsibilities Front-End/Digital design implementation of Sensor/Mixed signal digital blocks RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with SoC power management team for power sequencing requirements and system level considerations Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 8+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3068889 Show more Show less

Providing expertise for test solutions during design planning, budgeting, and implementation. MBIST implementation and validation, including BIST architecture planning, memory grouping, pattern generation, validation, silicon bring-up, diagnostics analysis, and debug. Participating in customer s design and flow reviews. Driving, prototyping, and developing new Design for Test methodologies. Multitasking across various issues and priorities to help customers exploit new technologies. Collaborating with Solution Architects to develop and productize next-gen test technologies. The Impact You Will Have: Enhancing Synopsys ability to deliver cutting-edge test solutions that meet customer needs. Contributing to the successful integration and silicon bring-up of complex digital ICs. Ensuring high customer satisfaction through effective technical support and problem resolution. Driving innovation in test methodologies and technologies. Supporting the development of next-gen test technologies that push the boundaries of whats possible. Playing a key role in winning new customers and expanding Synopsys market presence. What You ll Need: Minimum BS+10 years of relevant experience/MS+8 years of relevant experience in Electrical Engineering, Computer Engineering, or other relevant fields of study. Experience with RTL coding, DFT insertion, ATPG, MBIST architecture planning, insertion, validation, pattern generation, and silicon bring-up. Excellent knowledge of memory BIST flows, memory fault models, MBIST algorithms, hard/soft repair, and eFuse repair flow. Experience in handling memory BIST for large, complex SoCs with various IPs. Exposure to MBIST of automotive designs is a plus. Good understanding of protocols like 1149.1, 1500, 1687.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: An experienced Solutions Engineer with a proven track record in project execution and overall project management within the semiconductor industry You excel in deploying Synopsys DFT technologies on customer designs, ensuring projects are completed on schedule and with high quality You are adept at managing multiple projects simultaneously, recognizing and mitigating risks, and working proactively on contingency plans You possess exceptional verbal and written communication skills, leadership abilities, and a strong teamwork ethic Your proficiency in PowerPoint, Excel, and Word, along with your ability to work unsupervised, makes you a valuable asset to any team You have a solid background in the implementation of DFT technologies and are eager to work cross-functionally with internal teams, gaining exposure and visibility on a global scale throughout the organization, What Youll Be Doing: Deploying Synopsys DFT technologies on key customersdesigns and successfully executing the project, Acting as the focal point of contact and managing all external and internal communications across cross-functional teams, Planning and directing project schedules, identifying and escalating issues, and driving problems to resolution, Identifying and managing risks, ensuring the completion of projects on schedule and with high quality, Organizing interdepartmental activities and ensuring clear and concise communication, Working closely with internal teams (Applications Engineering, R&D) to meet customer requirements and achieve goals and targets, The Impact You Will Have: Ensure successful deployment of Synopsys DFT technologies on customer designs, Facilitate effective communication and coordination between cross-functional teams, Drive projects to completion, meeting deadlines and maintaining high standards of quality, Identify and mitigate risks to ensure project success, Contribute to the overall success of Synopsys by delivering high-quality solutions that meet customer needs, Enhance customer satisfaction and build strong, long-lasting relationships with key customers, What Youll Need: Solid background and proven track record in the implementation of DFT technologies, Experience in deploying Scan Compression, On-chip DFT Fabric, ATPG, Diagnosis, MemoryBIST, LogicBIST, and Boundary Scan, Proficiency in project management and the ability to manage multiple projects simultaneously, Exceptional verbal/written communication, leadership, interpersonal, and teamwork skills, Good working knowledge of PowerPoint, Excel, and Word, Who You Are: A detail-oriented and process-driven professional with a strong engineering background You possess excellent organizational skills and the ability to communicate effectively across various levels of the organization You are a proactive problem-solver who can work independently and within a team Your leadership abilities and teamwork ethic enable you to drive projects to successful completion, ensuring high-quality outcomes and customer satisfaction, The Team Youll Be A Part Of: You will be part of a dynamic and innovative team that focuses on deploying Synopsys DFT technologies to key customer designs This team works cross-functionally with internal teams such as Applications Engineering and R&D, and has a global presence within the organization Together, you will strive to meet customer requirements and achieve project goals, contributing to the overall success of Synopsys, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Greeting with HCL Tech! We were looking somebody who is having experience in DFT Experience: 4 to 10 Years Location: Kochi Hands-on experience with Scan, EDT, SSN insertion, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing. Hands-on Experience to do MBIST Insertion, Verification including Repair mode, Pattern generation. Spy Glass experience to resolve DFT DRC at RTL stage. SoC Translation flow, Patterns hand-off. Post Silicon Debug on Tester. Strong co-working experience with other dependent functions, Constraints development, STA & Physical Design. Should be able to handle team of 4-6 members. Drive team towards meeting Milestone in high pressure situation. Added advantage if Lead has executed 2-3 Projects in Intel flow.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years’ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG In depth knowledge of DFT concepts. In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. Expertise in scripting languages such as perl, shell, etc. Experience in simulating test vectors. Knowledge of equivalence check and RTL lint tool (like spyglass). Ability to work in an international team, dynamic environment Ability to learn and adapt to new tools and methodologies. Ability to do multi-tasking & work on several high priority designs in parallel. Excellent problem-solving skills Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076092 Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years’ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG In depth knowledge of DFT concepts. In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. Expertise in scripting languages such as perl, shell, etc. Experience in simulating test vectors. Knowledge of equivalence check and RTL lint tool (like spyglass). Ability to work in an international team, dynamic environment Ability to learn and adapt to new tools and methodologies. Ability to do multi-tasking & work on several high priority designs in parallel. Excellent problem-solving skills Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Your Impact Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Prior experience working with Gate level simulation, debugging with VCS and other simulators. Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Prior experience with Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Background in Test Static Timing Analysis Past experience with Post silicon validation using DFT patterns.

Alternate Job Titles: ASIC Design Engineer Digital Design Engineer Senior ASIC Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. PVT Sensor IP development is a critical offering for process, voltage, temperature, and other monitoring IPs within SOC subsystem. Synopsys is a market leader for these IP developments which are integral parts of Silicon lifecycle monitoring. You Are: As a new, exciting, and challenging position, we are looking for a talented person that can show a great level of initiative and ability to work in a busy and fast-changing environment. This rewarding role is fundamental to the successful and smooth operation of the engineering teams. You will play a vital role in helping to strengthen and develop forecasting capabilities, based upon improved monitoring capacity and forward-looking project schedules. You will generate test benches and test cases, perform RTL and gate-level SDF-annotated simulations and debug, and may perform mixed-signal (digital + analog) simulations and debug. You will interact with our application engineers and provide guidance to customers. Additionally, you will participate in the generation of data books, application notes, and white papers. What You’ll Be Doing: Generate test benches and test cases. Perform RTL and gate-level SDF-annotated simulations and debug. May perform mixed-signal (digital + analog) simulations and debug. Interact with our application engineers and provide guidance to customers. Participate in the generation of data books, application notes, and white papers. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Understand tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views. Write RTL Code, with solid Verilog, PERL, and Python skills, and TCL is a good addition. Understand static timing analysis and synthesis, DFT/ATPG skills would be a plus. Knowledge of any high-speed communication protocol is not mandatory but an asset. Previous knowledge in customer support and/or silicon bring-up is a plus. The Impact You Will Have: Strengthen and develop forecasting capabilities based on improved monitoring capacity. Ensure high-quality and reliable silicon lifecycle monitoring solutions. Enhance quality assurance methodology by adding more quality checks/gatings. Support internal tools development and automation to improve productivity across ASIC design cycles. Work with design engineers on new tools/technology and new features evaluation and adoption. Contribute to the successful and smooth operation of the engineering teams. What You’ll Need: Bachelor’s or master’s degree in electrical engineering or a related field. 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Who You Are: Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on developing cutting-edge PVT Sensor IPs integral to Silicon lifecycle monitoring. This team collaborates closely with other engineering teams to ensure the highest quality and performance of our products. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DFT Lead/Manager Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Minimum 10+ years of Experience in DFT/DFX. • Complete ownership of the DFT from Architecture to ATE Silicon Bringup support • Hands on experience in JTAG & IJTAG protocols, MBIST and scan architectures. • Verification skills including System Verilog, LEC and validating test timing of the design • Hands on in Scan Structure insertion in RTL • Handson in Mbist insertion • ATPG • Coverage • GLS in notiming & timing domain • Post Tapeout, Pattern delivery and Silicon bringup support • Understanding the testbench in System Verilog, UVM/VMM is addon • Strong verbal communication skills and ability to thrive in a dynamic environment • Good leadership skills and willing to drive a team of 5 to 6 young engineers • Knowledge of DDR IP Loop back test is an added advantage TekWissen Group is an equal opportunity employer supporting workforce diversity.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.Proven expertise in analysing and resolving DRCs/TSVs .Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .Hands on experience on industry standard tools used for DFT featuresProficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.Excellent analytical and problem-solving skills, with a keen attention to detail.Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design * Experience working with ATE engineers for silicon bring up, silicon debug and validation. * Experience in processor flow and post silicon validation Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.

Responsibilities DFT Engineer Bangalore, India 6+ years experience in DFT In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis Analyze design and propose best compression technique Debug and resolve the DRC issues Work with front end team to provide the solutions and make sure DFT DRCs are fixed Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is required In depth knowledge and hands on experience in MBIST insertion and Memory test validation Expertise in Mentor tools is plus Bachelors Degree in Electrical, Electronics or Computer Engineering Show more Show less

locationsIndia, Bangalore time typeFull time posted onPosted 9 Days Ago job requisition idJR0274850 Job Details: About The Role : We are looking for Senior DFT Design Engineers to join our team who are ready to make significant impacts in graphics and visual computing. As a member of the GHI DFT group, you will be responsible for one or more of the following activities: You will work on the design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG and/or DFT/JTAG controller You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types you are responsible for. Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration of the GPU block. Qualifications: The ideal candidate will exhibit the following traits/skills: Excellent written and verbal communication skills Demonstrate Leadership ability in driving execution Demonstrate teamwork, problem solving and influencing skills Ability to work with different geographical locations Minimum Qualifications: Bachelors in Electrical/Computer Engineering or related field with 9+ years of experience. Or a Masters in the same fields with 7+ Years of academic or industry experience. Your experience should be in following At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST) (This is a key skill requirement.) SoC or IP DFT design, integration or verification EDA tools such as ATPG tools, Siemens Tessent shell, VCS simulation and/or debug tools. Preferred Qualifications: Silicon enabling debug or test pattern development experience Design automation skills and proficiency in programming or scripting languages Structural design flows, including timing, routing, placement or clocking analysis High volume manufacturing requirements and test flows 3D, media and display graphics pipelines SoC architecture Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

General Summary: Qualcomm is a leading technology innovator driving next-generation experiences and digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systemsincluding digital, analog, RF, optical circuits, mechanical systems, equipment, packaging, test systems, FPGA, and DSPthat launch cutting-edge, world-class products. You will collaborate closely with cross-functional teams to develop solutions and meet rigorous performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of hardware engineering experience OR Master's degree in the relevant field with 2+ years of hardware engineering experience OR PhD in the relevant field with 1+ year of hardware engineering experience Minimum 5+ years experience in Design for Test (DFT), including ATPG, Scan Insertion, MBIST, and JTAG Core Skills & Experience: Deep knowledge of DFT concepts and hands-on experience with scan and MBIST insertion Expertise in ATPG pattern generation and verification, MBIST verification, and post-silicon bring-up and yield analysis Strong skills in defining test mode timing constraints and resolving timing violations with corrective actions Ability to design and analyze tests for new technologies, including custom RAM and RMA Proficient in scripting languages such as Perl and Shell for automation and tooling Experience simulating test vectors to verify test coverage and correctness Familiarity with equivalence checking and RTL lint tools like SpyGlass Ability to thrive in dynamic, international teams and adapt quickly to new tools and methodologies Strong multitasking abilities to manage multiple high-priority design projects simultaneously Excellent problem-solving skills with a proactive, analytical mindset