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design engineering power architecture verification software verilog systemverilog vhdl ip subsystems simulation debugging linting test synthesis timing analysis optimization support dft interface documentation coding electrical synopsys cadence graphics communication usb ethernet prototyping flow

Work Mode

On-site

Job Type

Contractual

Job Description

About The Job

At Minutes to Seconds, we match people with great skills with tailor-fitted jobs to achieve well-deserved success. We know how to match people to the right job roles to create that perfect fit. This changes the dynamics of business success and catalyzes the growth of individuals. Our aim is to provide both our candidates and clients with great opportunities and the ideal fit every time.We have partnered with the best people and the best businesses in Australia in order to achieve success on all fronts. We’re passionate about doing an incredible job for our clients and job seekers. Our success is determined by the success of individuals at the workplace.We would love the opportunity to work with YOU!!Minutes to Seconds is looking for a ASIC / SoC Design Engineer in Bangalore.

Requirements

About the RoleWe are seeking a highly skilled ASIC / SoC Design Engineer to join our hardware engineering team. The ideal candidate will be responsible for designing, implementing, verifying, and optimizing ASIC or System-on-Chip (SoC) solutions for high-performance, low-power applications. You will work closely with cross-functional teams including architecture, verification, physical design, and software teams to deliver world-class semiconductor products.Key Responsibilities
  • Collaborate with architects to define micro architecture specifications for ASIC/SoC designs.
  • Design RTL using Verilog / SystemVerilog / VHDL based on functional requirements.
  • Integrate IP blocks into SoC systems, including CPU cores, memory subsystems, and peripheral interfaces.
  • Conduct functional simulation, debugging, and linting to ensure design correctness.
  • Work with verification teams to develop and execute test plans.
  • Perform synthesis, timing analysis, and optimization for performance, power, and area (PPA).
  • Support DFT (Design for Test) and implement scan chains, BIST, and other test features.
  • Interface with physical design teams for floorplanning, place & route, and tape-out support.
  • Participate in design reviews and contribute to continuous improvement in design methodology.
  • Maintain thorough documentation of design specifications, coding standards, and processes.

Required Skills & Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
  • 3–8+ years of experience in ASIC or SoC digital design.
  • Strong RTL coding skills in Verilog / SystemVerilog / VHDL.
  • Solid understanding of SoC architecture, interconnects (AMBA, AXI, AHB, APB), and memory subsystems.
  • Experience with EDA tools such as Synopsys, Cadence, or Mentor Graphics for synthesis, simulation, and static timing analysis.
  • Knowledge of low-power design techniques (clock gating, power gating, multi-VDD).
  • Familiarity with DFT and scan insertion methodologies.
  • Strong problem-solving skills and ability to debug complex hardware issues.
  • Excellent verbal and written communication skills.

Preferred Skills

  • Experience with high-speed interfaces (PCIe, DDR, USB, Ethernet).
  • Knowledge of verification methodologies (UVM/OVM).
  • Experience with FPGA prototyping for ASIC/SoC designs.
  • Exposure to post-silicon bring-up and lab validation.
  • Understanding of physical design flow and PPA trade-offs.

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