ASIC Design Verification Engineer

Role Overview:

Senior ASIC Design Verification Engineers

Key Responsibilities:

• Develop and execute

  verification plans

  for SoC and IP-level designs.
• Build and maintain

  test benches

  using

  System Verilog and UVM

  .
• Perform

  functional verification

  , including simulation, coverage analysis, and debugging.
• Collaborate with design and architecture teams to ensure

  verification completeness

  .
• Automate verification flows using

  scripting languages

  (Python, Perl, Shell, etc.).
• Analyze and report

  coverage metrics

  and ensure compliance with verification goals.

Required Skills:

• 4-20 years experience in

  ASIC Design Verification

  .
• Strong knowledge of

  System Verilog

  and

  UVM methodology

  .
• Hands-on experience in

  SoC

  and

  IP-level verification

  across domains such as:

• Automotive

• Audio

• Networking

• High-Speed Interfaces

  (PCIe, Ethernet, USB)

• Memory Subsystems

  (DDR, LPDDR)

• Processor Subsystems

  (ARM, RISC-V)
• Proficiency in

  scripting languages

  (Python, Perl, Shell).
• Good understanding of

  verification concepts

  , coverage, and debugging techniques.

Good to Have:

• Exposure to

  C programming

  for embedded or verification-related tasks.
• Familiarity with

  formal verification

  and

  low-power verification

  methodologies.
• Experience with

  industry-standard EDA tools

  (Synopsys VCS, Cadence Xcelium, Mentor Questa).

Education:

Electronics, Electrical, or Computer Engineering