Analog Layout Engineer | Physical Design Engineer | AMS Layout Design

Acesoft Labs

3 - 8 years

15 - 27 Lacs

bengaluru

Posted:22 hours ago| Platform:

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Skills Required

mentor graphics calibre cadence custom layout analog layout physical design vlsi node lvs ams layout design verification flow layout verification lowers nodes mixed signal cmos tsmc hbm digital block drc analog design chip level repairing analog blocks ic mixed-signal

Work Mode

Work from Office

Job Type

Full Time

Job Description

Role & responsibilities

Description

4 to 8 years of experience in Design and development of critical analog, mixed-signal, custom digital block.
TSMC 16/12nm,7nm,5nm,3nm and below (foundries are also fine like Intel, Samsung, GF)
Preferably TSMC 5nm/3nm experience.
Responsible full chip level integration support.
Verification flows - LVS/DRC/DFM/Antenna check/EMIR experience.
Responsible for on-time delivery of block-level layouts of acceptable quality.
Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.
Analog blocks like Regulators/Charge pumps/Power Management etc..
HBM experience is an added advantage.

PLs share resumes/CV to pradeep.b@acesoftlabs.com

Preferred candidate profile

BE or MTech in Electronics/VLSI Engineering
Good communications skills as we work with cross-functional teams.
Good hands-on experience in recent times on lowers nodes.
Should work independently

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