Analog Layout Engineer | Physical Design Engineer | AMS Layout Design Acesoft Labs

3.0 - 8.0 years

15 - 27 Lacs

bengaluru

Work from Office

Role & responsibilities Description : 4 to 8 years of experience in Design and development of critical analog, mixed-signal, custom digital block. TSMC 16/12nm,7nm,5nm,3nm and below (foundries are also fine like Intel, Samsung, GF) Preferably TSMC 5nm/3nm experience. Responsible full chip level integration support. Verification flows - LVS/DRC/DFM/Antenna check/EMIR experience. Responsible for on-time delivery of block-level layouts of acceptable quality. Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. Analog blocks like Regulators/Charge pumps/Power Management etc.. HBM experience is an added advantage. PLs share resumes/CV to pradeep.b@acesoftlabs.com Preferred c...

Posted 1 month ago

AI Match Score

Apply

Analog Layout Engineer | Custom Layout Engineer | Mixed Signal Layout Acesoft Labs

3.0 - 8.0 years

10 - 20 Lacs

hyderabad

Work from Office

Role & responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Excellent problem-solving skills in physical verification of custom layout. Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. Ability to guide junior team-members in their execution of Sub block-level layouts & review critical...

Posted 1 month ago

AI Match Score

Apply

Ams Verification Engineer Proxelera

3.0 - 8.0 years

25 - 40 Lacs

hyderabad

Work from Office

BE/B.Tech in ECE /M.Tech in VLSI with 3 to 9 years experience in Analog Mixed Signal Verification Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks Very Good experience in Analog Mixed Signal verification simulation tools. Good experience in System Verilog, UVM methodologies Able to train the team members and guide them to the solutions for problems Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch. Good experience in Gate level netlist simulation Experience in Python, Perl, Shell scripting is added advantage. Good communication and documentation skills

Posted 1 month ago

AI Match Score

Apply

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.