13 Custom Layout Jobs

We are looking for an experienced IO Layout Engineer to join our team in Bangalore. The role involves custom IO layout design, optimization, and sign-off at advanced technology nodes. Responsibilities: Create and optimize IO circuit layouts including ESD structures and analog IOs. Perform floor planning, placement, routing, and parasitic extraction. Ensure DRC, LVS, ERC compliance using industry-standard tools. Collaborate with circuit and verification teams for sign-off. Automate layout flows using scripting for better productivity. Required Skills: 3-8 years in IO / Custom Layout. Strong knowledge of Cadence Virtuoso and Calibre/Assura verification. Experience with advanced nodes (28nm & below). Good understanding of device physics & IO design concepts. Scripting knowledge (Skill/Tcl/Perl/Python) preferred.

Expertise in working on memory layout design for advanced nodes (TSMC 3nm, 5nm,), including FinFET architecture and challenges such as variability and manufacturability Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness Expertise in performing debugging of silicon failures and identify layout-related issues Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA) Provide feedback on circuit designs to improve layout efficiency Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits) Automate repetitive tasks and improve workflow efficiency using scripting (eg Python, SKILL) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit Location - Bangalore, Beijing, Moscow, Romania, Taiwan

Expertise in working on memory layout design for advanced nodes (TSMC 3nm, 5nm,), including FinFET architecture and challenges such as variability and manufacturability Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness Expertise in performing debugging of silicon failures and identify layout-related issues Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA) Provide feedback on circuit designs to improve layout efficiency Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits) Automate repetitive tasks and improve workflow efficiency using scripting (e.g., Python, SKILL) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit. Location- Bengaluru, Taiwan,Beijing, Moscow, Romania

Qualcomm India Private Limited is seeking a Layout Engineer to develop block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. As a Layout Engineer, you will apply your understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using different tools and techniques to identify and troubleshoot issues, staying abreast of new verification methods. Collaboration with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues will be a key aspect of this role. The ideal candidate should possess a Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or a related field, with at least 2+ years of experience in designing custom layouts in a relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. Alternatively, an Associate's degree in Computer Science, Mathematics, Electrical Engineering, or a related field, with 4+ years of relevant experience, or a High School diploma or equivalent, with 6+ years of relevant experience will also be considered. Candidates should have 2+ years of experience using layout design and verification tools such as Cadence, LVS, and rmap. Additionally, 2-5 years of experience in Custom layout and Memory Layout design, including Memory Leafcell layout library design from scratch, top-level integration, knowledge of different memory architectures and compilers, optimized layout design for better performance, and expertise in Finfet technology and DRC limitations are desired. Proficiency in physical verification flow & debug, including DRC, LVS, ERC, Boundary conditions, Cadence Virtuoso layout editor, Calibre physical verification flow, SKILL, and PERL for custom tiling and automations is expected. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to disability-accommodations@qualcomm.com. Qualcomm expects its employees to comply with all applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use Qualcomm's Careers Site. For more information about this role, please contact Qualcomm Careers.,

We are in search of Salesforce Developers who possess a solid understanding of Apex, VisualForce, SOQL, and SOSL. Proficiency in Triggers, Workflows, ProcessBuilder development, batch jobs, custom objects, custom layout, test coverage, and Salesforce app development is essential. Your role will involve designing and coding solutions to address technical issues, crafting well-structured code, and engaging with clients. To be considered for this position, you should meet the following requirements: - 1 to 4 years of relevant experience - Completed a regular B.Tech. or MCA program - Demonstrated expertise in Salesforce development - Proficiency in object-oriented programming and MVC - Strong code debugging abilities - Possess good aptitude, a diligent work ethic, and a positive outlook - Excellent written and verbal communication skills in English If you meet the criteria mentioned above and are interested in this opportunity, please send an email to companyhr@webners.com. Kindly ensure to include your detailed resume as an attachment.,

You will be responsible for designing and developing critical analog, mixed-signal, custom digital blocks, and providing full chip level integration support. Your expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is crucial for this role. You will be required to perform layout verification tasks such as LVS/DRC/Antenna checks, quality assessments, and support documentation. Ensuring the on-time delivery of block-level layouts with high quality is a key aspect of your responsibilities. Your problem-solving skills will be essential for the physical verification of custom layouts. It is important to demonstrate precise execution to meet project schedules and milestones in a multi-project environment. You should possess the ability to guide junior team members in executing sub block-level layouts and reviewing critical elements. Additionally, contributing to effective project management and maintaining clear communication with local engineering teams are vital for the success of layout projects. The ideal candidate for this role should have a BE or MTech degree in Electronic/VLSI Engineering along with at least 5 years of experience in analog/custom layout design in advanced CMOS processes.,

As an IC Layout Manager at Micron Technology, you will have the opportunity to lead a dedicated team in India focused on designing IC layouts for cutting-edge applications such as artificial intelligence and high-performance computing solutions like High Bandwidth Memory. Your role will involve collaborating with teams across Micron's global network to ensure the timely delivery of multiple projects. Your responsibilities will include building and developing a custom layout team to support Micron's DRAM layout requirements, overseeing the development of analog and custom layouts, and training team members in technical skills. Effective communication with engineering teams in different countries, organizing tasks and resource allocations, managing team performance, and contributing to the success of Micron's DRAM operations in India will be crucial aspects of your role. To be successful in this position, you should have at least 14 years of experience in analog/custom layout within advanced CMOS processes, with expertise in tools such as Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS. Strong layout and floor planning skills, as well as experience in managing multiple custom IC layout projects, are essential qualifications. Additionally, you should possess excellent communication skills, the ability to work effectively in a fast-paced environment, and a passion for innovation and team development. Ideally, you should hold a BE or MTech in Electronic/VLSI Engineering. Previous experience in DRAM/NAND layout design is desirable but not mandatory. Your role will involve collaborating with overseas teams, defining strategies, and ensuring the successful implementation of technical solutions by your team. Micron Technology, Inc. is a global leader in memory and storage solutions, driving innovation and transformation in the data economy. Through a focus on customer needs, technology leadership, and operational excellence, Micron delivers high-performance DRAM, NAND, and NOR memory and storage products that power advancements in artificial intelligence and 5G applications. If you are passionate about driving innovation, fostering team growth, and contributing to the evolution of information technology, consider joining Micron Technology and be part of a dynamic and forward-thinking organization. To learn more about Micron Technology, Inc. and explore career opportunities, please visit micron.com/careers. For any assistance with the application process or to request accommodations, please contact hrsupport_india@micron.com. Micron upholds a commitment to ethical labor practices and prohibits the use of child labor, adhering to all relevant laws and standards.,

As an IC Layout Manager at Micron Technology, you will have the opportunity to work with a talented core team based in India, focusing on designing IC layouts for applications such as artificial intelligence and high-performance computing solutions, including High Bandwidth Memory. Your role will involve collaborating with global teams to ensure the successful completion of multiple projects within scheduled milestones. Your responsibilities will include: - Building and growing a Custom layout team to support Micron's global DRAM layout requirements. - Developing Analog and custom layout designs to meet project schedules and milestones. - Training team members in technical skills and fostering a healthy team culture. - Communicating effectively with engineering teams across different regions to ensure project success. - Organizing, prioritizing, and managing tasks and resources for multiple projects. - Performance management and development of team members. - Leading hiring and retention efforts. - Contributing to the overall success of Micron's DRAM India operation. To qualify for this role, you should have: - 14+ years of experience in analog/custom layout in advanced CMOS processes. - Minimum 1+ year of people management experience. - Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS. - Strong skills in layout, floor planning, and manual routing. - Ability to build and develop a premier analog/mixed-signal layout team. - Experience in managing multiple Custom IC layout projects. - Motivation, attention to detail, and a systematic approach in IC layout design. - Excellent communication skills and the ability to work effectively in a team and fast-paced environment. - Strong analytical skills, creative thinking, and self-motivation. - Capability to work in a cross-functional, multi-site team environment. - Previous experience in DRAM/NAND layout design is desirable. - Passion for attracting, hiring, and retaining engineers with an innovative mindset. - Collaboration skills with overseas teams to define and execute strategies across the organization. - Accountability for the technical solutions implemented by your team. Education requirements for this role include a BE or MTech in Electronic/VLSI Engineering. Micron Technology, Inc. is a global leader in innovative memory and storage solutions, dedicated to transforming information usage for the betterment of all. Through a focus on technology leadership and operational excellence, Micron delivers high-performance memory and storage products that drive advancements in artificial intelligence and 5G applications. For more information about Micron Technology, Inc., please visit micron.com/careers. If you require assistance with the application process or need reasonable accommodations, please contact hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and adheres to all relevant labor laws, regulations, and international standards.,

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. • Contribute to effective project-management. • Effectively communicating with Local engineering teams to assure the success of layout project. Educational Background • BE or MTech in Electronic/VLSI Engineering • 3 + year experience in analog/custom layout design in advanced CMOS process. NOTE: **custom layout or analog layout with TSMC 3nm/5nm7nm & 5+ exp ****

Company Overview Connectpro operates in the human-resources industry, specializing in recruitment and talent acquisition. Role And Responsibilities As a senior analog design engineer at Connectpro, you will be responsible for taking a subsystem of analog design through all phases of the design process. This includes: Creating the architecture of the analog subsystem Providing technical leadership to the team during execution Designing, simulating, and supervising the layout and verification processes Evaluating and debugging silicon samples You will be working with the latest Cadence analogue design tools including Virtuoso Composer, Verilog, HSPICE, and other PC-based tools like Matlab. The circuits you will be working on involve mixed signal blocks such as switched capacitor amplifiers, PLL, RAM, high-speed interfaces, references, IO circuits, data converters, and digital building blocks. Your role will also involve ensuring timely execution and collaborating with cross-functional teams like PE/TE. Experience with custom layout and analog verification is a plus. Candidate Qualifications To be successful in this role, you should possess the following qualifications: Bachelor's degree with 5-8 years of experience in CMOS, analog/power/mixed-mode IC design using tools similar to the ones mentioned above Strong fundamentals in CMOS analog design Excellent communication skills Ability to interact effectively with cross-functional teams Understanding of the semiconductor development flow Skills: hspice,semiconductor development flow,adc,,pll,icdesign,data converters,analog,layout/verification,dac,mixed signal,team management,cadence analogue design tools,custom layout,analog/power/mixed-mode ic design,simulation,evaluation/debug,amplifiers and filters,matlab,interact with cross functional teams,switched capacitor amplifiers,pmic,cmos process,cmos,,ram,ams,virtuoso composer,architecting,design,dll,,digital building blocks,references,analog verification,cmos,io circuits,hispeed interfaces,communication skills,verilog,analog design,

Job Specs : We are seeking a highly skilled and motivated Analog Circuit Designer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of Analog / Mixed Signal IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Desired Profile : Bachelor's / Master's degree in engineering from EEE / E&C with 4+ Years of work expertise in mixed-signal or CMOS circuit design Expertise in analog blocks like power management DC-DC convertor, LDOs or Expertise in designing ADC / DAC/ PLLs or Experience in simulation or characterization of IO cells Design and architect CMOS analog and mixed-signal integrated circuits Simulate designs with state-of-the-art CAD tools Document designs and simulation results Experience with high-speed SERDES circuits Knowledge of layout issues Experience with circuit simulators (HSPICE, Spectre, etc) Experience with Cadence Design Environment is an asset Working knowledge of PERL and UNIX shell scripting languages is an asset Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. NOTE : Preferred resources holding valid regional work permits only Location : Moscow, USA,Bengaluru,Hubli,Kolkata

Greetings from ||Thundersoft|| We are looking for Cutsom Layout engineers with an exposure of Custom layout and having experience in GF 22nm FDSOI technology node

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in Analog Layout design Expertise in planar technology node / higher node 180 nm is mandatory Expertise in EMIR analysis, ESD, antenna and related layout solutions Knowledge of advanced technology nodes (7nm & below) Good understanding of advanced semiconductor technology process and device physics Full-custom circuit layout/verification and RC extraction experience Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit Location - Bangalore, Beijing, Taiwan, Vietnam