Testability Engineer (DFT)

10 years

0 Lacs

Posted:1 month ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

About the Company



We are a leading technology company dedicated to innovation and excellence in the field of semiconductor design and testing. Our mission is to provide cutting-edge solutions that enhance the performance and reliability of electronic devices. We foster a collaborative and inclusive culture that values diversity and encourages professional growth.



About the Role



DFT Engineer



Responsibilities



  • Develop and implement scan architectures (full scan, partial scan, compression).
  • Perform scan insertion, clock-domain handling, and scan chain stitching.
  • Design and integrate JTAG (IEEE 1149.x) architecture.
  • Implement LBIST (Logic Built-In Self Test) and MBIST (Memory BIST) solutions.
  • Create and optimize ATPG (Automatic Test Pattern Generation) for stuck-at, transition, path-delay, and advanced fault models.
  • Perform DFT rule checks (DRC) and ensure DFT signoff criteria are met.



Qualifications



  • Experience:

    8–10 Years

  • Location: Noida



Required Skills



  • DFT Tools Knowledge
  • Timing, linting, Synopsys RTL & Debug Skills
  • Verilog/VHDL RTL, Simulation, SDF, post silicon



Preferred Skills



  • Experience with advanced fault models and DFT methodologies.



Pay range and compensation package



Competitive salary based on experience and qualifications.



Equal Opportunity Statement



We are an equal opportunity employer and are committed to creating a diverse and inclusive workplace. We encourage applications from all qualified individuals regardless of race, gender, age, sexual orientation, disability, or any other characteristic protected by law.

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