Senior/Principal ASIC RTL Design Engineer (SoC/Subsystem)

As a Senior/Principal ASIC RTL Design Engineer at our company, you will have the opportunity to own end-to-end RTL design for complex SoC or large subsystem blocks. You will be involved in defining micro-architecture from specs, writing high-quality synthesizable SystemVerilog/Verilog RTL, and ensuring successful tapeout and silicon bring-up. **Responsibilities:** - Define micro-architecture and write synthesizable RTL for SoC-level or large subsystems. - Own design bring-up, integration, and work closely on timing, power, and area considerations. - Drive design reviews, bug resolution, and provide support for silicon validation and post-silicon debug. - Collaborate with DV team on test plans, assertions, and coverage goals. **Qualifications Required:** - 8+ years of hands-on ASIC RTL development experience with multiple production ASIC tapeouts. - Strong skills in SystemVerilog/Verilog RTL, micro-architecture, clock/reset design, low-power techniques, and bus protocols. - Experience collaborating with physical design on synthesis constraints, timing closure, DFT hooks, and ECOs. - Proven silicon bring-up experience for owned blocks/subsystems. **Nice to have:** - Exposure to coherency protocols, cache/memory controllers, DDR/PCIe subsystems, security/crypto blocks. - Skills in SVA for design-level assertions, performance modeling, or power/perf analysis. - Proficiency in scripting for design productivity using Tcl/Python. Thank you for considering this exciting opportunity to contribute your expertise to our team.,