Senior Design Verification Engineer

About Scaledge:

Scaledge is one of the fastest growing product engineering services companies focused on Semiconductor Chip - Design & Verification, Processors, System design and related Embedded Software development for domains like Storage, RISC-V, AI/ML, Automotive, Consumer, Networking and IoT. We are headquartered in Silicon Valley, USA with multiple design centers across India, UK and Canada.

Scaledge has a strong history of technology, methodology & domain expertise in IP/ASIC/SOC verification in Storage, Networking, Mobile & Consumer industry

About Opportunity:

Scaledge is looking for experienced, talented Verification Engineers (ASIC/IP/SOC/CPU/GLS) for dynamic and innovative Team. As a member of the team, you will be responsible for verifying the design, architecture and micro-architecture using advanced verification methodologies

Requirements

• Experience 5+ years.
• Hiring for Senior Engineer, Technical Lead, and Architect levels
• Dedicated/hands-on ASIC/IP/SOC DV experience.
• Experience working on block level UVM test benches - writing drivers, scoreboards, sequences,

constraints, and functional coverage models

• Strong interest in understanding the architectural and micro-architectural details of a design.
• Strong interest in debugging complex issues
• Drive and adopt new verification methodologies to improve effectiveness and efficiency
• Experience working on the memory subsystem is a plus

Responsibilities

• Build UVM test benches and own the verification of an IP from start to finish. Create coverage driven verification plans from specifications. Execute, review and refine to achieve coverage targets.
• Set up regressions and triage failures. Debug and drive any design and verification bugs found, to closure.
• Work with the team to improve DV methodology and infrastructure.

Required Skills

• Strong knowledge of Verilog, System Verilog, and Object-Oriented Programming
• Experience with modern verification techniques, especially including System Verilog, UVM, constraint-random and functional coverage methodologies
• Complete understanding of verification life cycle and ability to create of comprehensive verification plans
• Knowledge of high-speed PCIe, DDR, USB, AXI, APB, AHB protocols
• Experience verifying networking protocols such as Ethernet is a plus
• Experience with scripting languages such as Python, Tcl, or Perl
• Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out
• Strong technical writing and verbal communication skills

Education

• BTech/MTech in Electronic/Microelectronics, Electrical Engineering or Computer Science. Other Science graduates would be considered if they have relevant experience.