RTL Lead VLSI

Capgemini

8 - 13 years

30 - 40 Lacs

hyderabad pune bengaluru

Posted:1 month ago| Platform:

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Skills Required

cdc asic verilog rtl coding rtl design python asic synthesis architecture shell scripting lint vlsi design soc design vhdl synthesis spyglass perl ip development

Work Mode

Hybrid

Job Type

Full Time

Job Description

Title- RTL Technical Lead- VLSI Design

Experience:

RTL Lead

Roles and Responsibilities

Lead RTL design and integration of complex SoC architectures using Verilog/SystemVerilog.
Own and execute SoC integration tasks including IP stitching, bus protocols, and top-level connectivity.
Perform static checks using
SpyGlass Lint
,
CDC analysis
, and
DC Synthesis
.
Collaborate with cross-functional teams including verification, physical design, and DFT.
Develop automation scripts using
TCL, Perl, Python, or Shell
to optimize design flows.
Ensure design quality through thorough reviews, documentation, and compliance with SoC flow standards.
Work with tools like
VCLSP
for low-power design and verification.
Mentor junior engineers and contribute to technical leadership within the team.

Desired Candidate Profile

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field.

Primary Skills:

Please share cv at archana.tomar@capgemini.com

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