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Home
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ACL Digital
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Physical Verification Engineer

Physical Verification Engineer

ACL Digital

4 years

0 Lacs

Bengaluru Karnataka India

Posted:3 weeks ago| Platform:

Apply

Skills Required

verification design drc lvs checks analyze layout circuit interface interpretation support automate efficiency development electrical debugging scripting flow technology integration electromigration dfm

Work Mode

On-site

Job Type

Full Time

Job Description

Job Title:

Experience:

Location:

Employment Type:

Industry:

Job Summary:

Physical Verification Engineer

Key Responsibilities:

Own and execute block-level and full-chip
DRC
,
LVS
,
ERC
,
Antenna
, and
Density
checks.
Analyze physical verification violations and debug layout/schematic mismatches.
Work closely with layout, circuit design, and digital backend teams to ensure verification closure.
Develop and maintain PV rule decks (if applicable) and flows.
Interface with foundries (e.g., TSMC, Samsung, GlobalFoundries) for rule interpretation and deck issues.
Support tapeout preparation and signoff activities.
Automate PV flows and improve runtime efficiency through scripting.
Contribute to PV methodology development and cross-functional training.

Required Skills and Experience:

B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Design.
4+years of hands-on experience in physical verification.
Strong experience with
Calibre (Mentor/Siemens)
or
Assura/PVS (Cadence)
for DRC/LVS/ERC.
Familiarity with
GDSII/OASIS
layout formats and layout hierarchy handling.
Knowledge of layout design principles and basic CMOS concepts.
Good debugging and analytical skills.
Scripting knowledge in
Tcl
,
Python
, or
Perl
for flow automation.

Preferred Qualifications:

Experience working at advanced technology nodes (7nm, 5nm, 3nm).
Exposure to full-chip integration and signoff tapeouts.
Familiarity with foundry PV rule decks and process guidelines.
Knowledge of electromigration (EM), IR drop, or DFM checks is a plus.

Interested can share Cv to Sharmila.b@acldigital.com

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