Physical Design Manager

10 years

0 Lacs

Posted:1 day ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

www.Sevyamultimedia.com

Physical Design Manager / Senior Manager

About Us

We are a technology consulting company delivering best-in class Chip Design Services.

Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow.



With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills



Approach

We support a mix of engagement models to support diverse client requirements.

Engagement Models


Turnkey (SoW) Engagement


Staff Augmentation (T&M)


Offshore Design Center


Key Enablers

Hands on Leadership

Proven Industry Experts

TSMC DCA Parternship

Collaboration with Academia


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Physical Design Manager


Job Summary:

We are looking for an ASIC Physical Design Lead with extensive experience in timing closure and full-chip physical design. The candidate should be adept at interacting with the packaging team and managing tasks such as pads log, bump placement, and RDL routing.


Key Responsibilities:

  • Lead the physical design of complex ASIC projects from Netlist to GDSII.

  • Perform timing closure tasks including synthesis, place and route, and static timing analysis.

  • Oversee full-chip physical design processes, including floor planning, power grid design, clock tree synthesis, and signal integrity analysis.

  • Collaborate with the packaging team to ensure seamless integration of the chip design with the package, including pads log management, bump placement, and RDL routing.

  • Mentor junior engineers and guide them on physical design methodologies.

  • Drive innovation and efficiency in physical design workflows.


Qualifications:

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

  • Minimum of 10 years of experience in ASIC physical design.

  • Expertise in industry-standard EDA tools for physical design and verification.

  • Strong understanding of timing closure techniques and challenges.

  • Experience with full-chip design and familiarity with multi-voltage and multi-clock domain designs.

  • Excellent problem-solving and analytical skills.

  • Strong communication and leadership abilities.



Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

"Mining The Knowledge Community"

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