Lead RTL Design Engineer – ASIC / SoC / IP

8 - 13 years

15 - 25 Lacs

Posted:1 week ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

We are looking for a Lead RTL Design Engineer to drive micro-architecture and RTL development for ASIC, SoC, Sub-System, and IP designs. The ideal candidate will own complex design blocks, lead technical decisions, and collaborate closely with verification and physical design teams to deliver highquality silicon.

Key Responsibilities

  • Lead RTL design and development for ASIC / SoC / IP / Sub-System blocks
  • Define and own micro-architecture specifications aligned with system requirements
  • Perform RTL coding using industry best practices (synthesizable, scalable, reusable)
  • Drive design reviews, code quality, and lint/CDC/RDC closure
  • Collaborate with Design Verification for testbench development and debug
  • Work closely with Physical Design to ensure timing, power, and area closure
  • Support synthesis, ECOs, and tape-out activities
  • Ensure compliance with protocol specifications and architecture guidelines
  • Mentor junior RTL engineers and provide strong technical leadership

Key Expertise / Skills

  • Strong hands-on experience in RTL Design and RTL Coding
  • Deep knowledge of micro-architecture design
  • Experience across ASIC, CPU, GPU, SoC, IP, and Sub-System designs
  • Solid understanding of synthesis, timing, power, and area trade-offs
  • Proficiency in Verilog / SystemVerilog
  • Experience with lint, CDC, RDC, and low-power methodologies (UPF/CPF)
  • Protocol Experience (Mandatory / Preferred)
  • Hands-on design experience with one or more of the following protocols:
  • PCIe
  • Ethernet
  • USB
  • Added Advantage
  • Prior experience in Sub-System (SS) design is a strong plus
  • Leadership & Collaboration
  • 2-4 years of proven leadership experience in RTL Design
  • Ability to own deliverables, drive schedules, and lead design teams
  • Strong communication and cross-functional coordination skills

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