SDC, Synthesis and STA Engineer

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SDC, Synthesis and STA Engineer

THE ROLE:

The focus of this role is to plan and execute the front end implementation of IPs and its closure. This involves ownership of SDC development, SDC generation, verification, promotion/demotion and equivalence checking. The role might also epxand to (if needed) synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on technical issues.

KEY RESPONSIBILITIES:

• Main responsibility is to own constratins, SDC developement for IPs, SS and SoCs. Including SDC generation, verification, promotion, demotion and equivalence using third party or self built tools.
• Additonal responsibilities for front end implementation of IPs might include synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure
• Collaborate with designer and PNR teams to achieve closure.
• Understand duration required, plan and execute as per schedule.
• Complete quality delivery for synthesis and timing closure.
• Debug and resolve technical issues

PREFERRED EXPERIENCE:

• Existing SDC, constraints development with or without using fisthail, excellicon or TCM.
• Experienced in synthesis, LEC, CLP and timing closure
• Preferred top level or SOC level experience
• Have handled blocks with complex designs, high frequency clocks and complex clocking
• complete understanding of timing constraints, low power aspects and concepts of DFT
• Have debug experience to solve issues.
• Interst in AI, Scripting and automation

ACADEMIC CREDENTIALS:

• Bachelors with 4 years of experience or Masters degree with 2 years of experience in Electrical Engineering

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