Soc Design Engineer

W Beyond

6 - 8 years

15 - 25 Lacs

hyderabad

Posted:4 days ago| Platform:

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Skills Required

soc design verilog rtl system verilog

Work Mode

Work from Office

Job Type

Full Time

Job Description

Key Responsibilities:

Design and integrate ARM - based subsystems derived from Arm Corestone reference packages into Azimuth AI Socs.
Implement and modify RTL for CPU subsystems, AMBA interconnects, memory controllers, and peripheral IP.
Collaborate with architecture teams on feature definition, microarchitecture updates, and performance targets.
Work closely with verification teams to debug functional issues and ensure high - quality coverage closure.
Support synthesis, timing analysis, and physical design teams during Soc execution.
Drive documentation, design reviews, and bring - up support for early silico and emulation platforms.
Contribute to methodology improvements for subsystem integration and design scalability.
Strong knowledge of ARM architecture, AMBA protocols (AXI, AHB, APB), and system - level integration.
Proficiency in RTL design(SystemVerilog/Verilog) and Soc integration flows.
Strong debugging skills across simulation, lint, CDC and synthesis environments.
Ability to collaborate in a fast-paced, cross - functional engineering environment.

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