Lead Physical Design Engineer

As an experienced Physical Design Engineer, your role will involve top-level floor planning, PG Planning, partitioning, placement, scan-chain reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks including timing and functional ECOs. You should have hands-on experience working on 65nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias. Your key responsibilities will include: - Providing technical guidance and mentoring to physical design engineers. - Collaborating with front-end ASIC teams to resolve issues. - Implementing Low Power Design techniques like Voltage Islands, Power Gating, and Substrate-bias. - Ensuring timing closure on DDR2/DDR3/PCIE interfaces. - Conducting floor planning, P&R, extraction, IR Drop Analysis, Timing, and Signal Integrity closure. - Utilizing Cadence, Synopsys, or Magma physical design tools effectively. - Proficiency in scripting languages like PERL, TCL. - Demonstrating strong Physical Verification skills. - Performing Static Timing Analysis using Primetime or Primetime-SI. Your qualifications should include: - 7 to 12 years of experience in ASIC Physical Design. - Strong background and detailed knowledge in physical design tools. - Excellent written and oral communication skills. - Ability to document plans clearly. - Experience with Logical vs. Schematic (LVS) checks, Antenna checks is a plus. This job is located in Hyderabad. As an experienced Physical Design Engineer, your role will involve top-level floor planning, PG Planning, partitioning, placement, scan-chain reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks including timing and functional ECOs. You should have hands-on experience working on 65nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias. Your key responsibilities will include: - Providing technical guidance and mentoring to physical design engineers. - Collaborating with front-end ASIC teams to resolve issues. - Implementing Low Power Design techniques like Voltage Islands, Power Gating, and Substrate-bias. - Ensuring timing closure on DDR2/DDR3/PCIE interfaces. - Conducting floor planning, P&R, extraction, IR Drop Analysis, Timing, and Signal Integrity closure. - Utilizing Cadence, Synopsys, or Magma physical design tools effectively. - Proficiency in scripting languages like PERL, TCL. - Demonstrating strong Physical Verification skills. - Performing Static Timing Analysis using Primetime or Primetime-SI. Your qualifications should include: - 7 to 12 years of experience in ASIC Physical Design. - Strong background and detailed knowledge in physical design tools. - Excellent written and oral communication skills. - Ability to document plans clearly. - Experience with Logical vs. Schematic (LVS) checks, Antenna checks is a plus. This job is located in Hyderabad.