8.0 - 20.0 years

0 Lacs

hyderabad, telangana

On-site

You should possess a B.Tech/M.Tech degree in Electronics and Communication Engineering with 8 to 20 years of experience in physical design of semiconductor chips. The role is based in Hyderabad and follows a general shift schedule with no work from home option. Your responsibilities will include top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks such as timing and functional ECOs, SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. You must have prior experience working on 65nm or lower node designs, implementing advanced low-power techniques like Voltage Islands, Power Gating, and substrate-bias. In this role, you will provide technical guidance and mentorship to physical design engineers, interface with front-end ASIC teams to resolve issues, and focus on low-power design techniques including Voltage Islands, Power Gating, and Substrate-bias. You should have expertise in timing closure on DDR2/DDR3/PCIE interfaces, excellent communication skills, and a strong background in ASIC Physical Design encompassing Floor planning, Place & Route, extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Additionally, you should have extensive experience and detailed knowledge in physical design tools such as Cadence, Synopsys, or Magma, proficiency in scripting languages like PERL and TCL, and a strong skillset in Physical Verification. Familiarity with Static Timing Analysis using Primetime or Primetime-SI is required. Your written and oral communication skills should be excellent, with the ability to clearly document plans and effectively collaborate with cross-functional teams while prioritizing work based on project requirements.,

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