Lead Design Verification Engineer

Lead Design Verification Engineer – PCIe Gen5/6

Location: Noida, India 

Experience: 6+ years 

Role summary

Lead

Key responsibilities

• Lead verification of

  PCIe Gen5/Gen6 IP/subsystem

  s using SystemVerilog and UVM.  
• Architect and maintain UVM environments, sequences, scoreboards, and coverage for PCIe-based designs.  
• Define test plans, drive constrained-random and directed testing, and achieve coverage closure.  
• Debug complex protocol and RTL issues, collaborating with design and architecture teams.  
• Mentor junior DV engineers and contribute to methodology and flow improvements. 

Required skills

• 6+ years of ASIC/SoC design verification experience with a strong focus on

  PCIe Gen5/Gen6.

• Strong 

  SystemVerilog

   and UVM knowledge, including environment architecture and coverage-driven verification.  
• Solid understanding of PCIe protocol concepts (LTSSM, link training, flow control, TLP/DLLP, config, error handling).  
• Hands-on experience with major simulators (e.g., VCS/Questa/Xcelium) and scripting for regressions.  
• B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or Computer Engineering.  

Company Description:

Silicon Patterns is a specialized engineering services company offering end-to-end semiconductor and embedded system solutions, including Design Verification (DV), RTL Design, SystemC Modeling, Emulation, Physical Design (PD), and Pre- & Post-Silicon Validation. Based in Hyderabad, with offices in Bengaluru and Raipur, and an engineering presence in Malaysia, the company serves global clients through flexible engagement models. Focused on VLSI and Embedded Systems, Silicon Patterns excels in industries such as Wireless, IoT, and Automotive, and works on cutting-edge technologies like AI/ML, edge computing, and HBM3/3E workloads. The company is committed to technical excellence while promoting a healthy work-life balance for its employees.