Role & responsibilities Job Description- REQUIRED KNOWLEDGE, SKILLS, AND ABILITIES : • Work experience with node 7nm or lower node designs with advanced low power techniques is must. • Experience on ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, Physical Verification are essential part of the job. • Well versed with Cadence or Synopsys tools is important. • Experience with Static Timing Analysis in Primetime or Primetime-SI is important. • Hands-on experience in scripting languages such as PERL, TCL is important. • Timing closure on high-speed interfaces is a plus. • Knowledge on Full chip Physical Design is beneficial. • Good ASIC fundamentals and problem-solving skills is preferred. MANDATORY SKILLS: • Experience with 7nm node. • Experience with Cadence Innovus Preferred candidate profile
Job Summary: Participate in the feature design and early development of software from a QA standpoint, in order to understand and prevent bugs from being developed into the software from its inception. Duties/Responsibilities: Establish hybrid cloud testbeds to connect subnets between on-premise network and a VPC in AWS / Azure / GCP cloud platform. Design, develop and fix automated test scripts using Python or Go for the Aviatrix enterprise cloud defined network software. Ensure that GUI and APIs are functional in each release by designing, developing, and performing automated testing in Python to reduce repeated manual testing in the same areas and increase overall test coverage. Improve the CI/CD pipeline by stabilizing regression tests, triaging regression failures, and categorizing them into different buckets. Follow up with development teams to resolve the issue. Monitor performance numbers in each release and benchmark performance for different cloud platforms against other competitors using completed testing script. Build and use lab environments to simulate and debug customer networking configurations (e.g., routers, firewalls). Perform live troubleshooting, log analysis, and issue reproduction, for customer QA issues. Required Skills/Abilities: Demonstrate independent ability to solve problems. Frequent use and application of basic technical standards, principles, theories, concepts and techniques. Provide solutions to a variety of technical problems of moderate scope and complexity. Effectively write automated tests to cover code development. Excellent verbal and written communication skills. Excellent interpersonal skills. Python or Go Minimum Requirements: Education: Bachelors degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field. Experience: Two (2)+ years of experience in the job offered or in a software engineering-related occupation. Skills: Minimum two years of experience required in each of the following skills: networking protocols and cloud native architectures; software defined networking and cloud networking; debugging of Linux networking stack; performance benchmarking and system testing; platform and infrastructure development and testing with high-speed networking protocols; distributed computing; object-oriented Python; Go; Git version control to maintain large software codebases
Role & responsibilities Job Responsibility As the Lead, you will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, test cases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support. You will work very closely with the Architecture, RTL/uArch, and cross-functional teams. Areas of focus: Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with the RTL/uArch team. Job Requirements Experience with block level, cluster level or chip/SoC level verification. Should be a self-starter. Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog. Expertise in scripting languages, python or perl. Strong experience in helping emulation and validation. Experience with modeling various HW blocks, IPs for verification, emulation. Ability to analyze systems-level performance, profiling, and analysis. Post silicon support Preferred candidate profile
Role & responsibilities Roles & Responsibilities: Develop user-friendly interfaces and components for the Apps Portal using React.js / Angular / Node (project-specific). Ensure a seamless, intuitive, and consistent user experience across the platform. Collaborate with the backend team to integrate RESTful APIs and manage data flow. Create responsive layouts and ensure compatibility across devices and browsers. Maintain clean, scalable, and reusable code following industry best practices. Implement role-based access control and dynamic UI rendering based on user roles. Optimize performance and loading speed of the portal. Skills & Qualifications: Solid understanding of HTML5, CSS3, JavaScript (ES6+). Experience with React.js (preferred) or Angular / Node. Familiarity with responsive design, component-based architecture, and UI libraries like Material UI, TailwindCSS, or Bootstrap. Experience working with REST APIs and JSON data structures. Proficiency in Git, basic knowledge of CI/CD, and code collaboration tools. Good problem-solving skills and attention to UI/UX details. Good to Have (Optional): Knowledge of TypeScript and modern JS patterns. Experience with state management (e.g., Redux, Context API). Basic understanding of authentication flows (OAuth, JWT). Exposure to Agile methodology and working in a sprint-based environment. Preferred candidate profile
As an Analog Design Engineer at Sykatiya Technologies, you will be an integral part of our highly talented team that focuses on Technical Ability and a positive Attitude. Your contributions to projects will reflect our commitment to excellence for our customers. Our team consists of skilled engineers and experts in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are looking for an Analog Design Engineer with 3-12 years of experience to join our team in Bangalore. The ideal candidate will have experience in transceiver design for high-speed interfaces such as DDR, HBM, PCIe, USB3, and JESD204. Exposure to nodes below 22nm is a plus, along with experience in FINFET technology and the 32G-112G range of SERDES. In this role, you will be responsible for taking at least one block from circuit design to layout closure. You should also be able to guide the layout team in high-performance matched circuit design. Understanding reliability requirements such as ESD, EMIR, EOS, Aging, and being able to work independently while mentoring junior team members are essential qualities we are looking for. If you have exposure to post-silicon validation, it would be considered a plus. Join us at Sykatiya Technologies and be part of a dynamic team that values technical expertise, a positive attitude, and a commitment to excellence in Analog Design.,
Build your career with Sykatiya Technologies! Sykatiya Technologies values both technical ability and the attitude of its highly talented team, which is evident in their contributions to customer projects. The team consists of skilled engineers and experts specializing in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are currently looking for an Analog Design Engineer with 3-12 years of experience to join our team in Bangalore. The ideal candidate will have experience in transceiver design for high-speed interfaces such as DDR, HBM, PCIe, USB3, and JESD204. Exposure to nodes below 22nm is a plus, as well as experience in FINFET technology and the 32G-112G range of SERDES. The successful candidate should have taken at least one block from circuit design to layout closure and be capable of guiding the layout team for high-performance matched circuit design. Understanding reliability requirements such as ESD, EMIR, EOS, Aging, etc., is essential. The candidate should be able to work independently, mentor juniors, and have exposure to post-silicon validation. If you are a motivated Analog Design Engineer looking to work with a team of experts and contribute to cutting-edge projects, we encourage you to apply and be a part of our innovative team at Sykatiya Technologies.,
Build your career with Sykatiya Technologies. Sykatiya Technologies values technical ability and attitude within its highly talented team, which is reflected in the contributions made to customer projects. The team consists of skilled engineers and experts specializing in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. This position is for IP/SOC/ASIC Verification with a required experience level of 3-20 years. The location for this role is in Bangalore & Hyderabad. As a member of the ASIC verification team, you will be responsible for the functional verification of ASIC IPs. The verification methodology utilizes advanced techniques and tools such as coverage-driven constrained random verification and formal verification. Object-oriented architectures and frameworks play a crucial role in the design and implementation of verification environments. The ideal candidate will possess expertise and aptitude in verifying functions like image processing, video compression, and computer vision. Additionally, as a verification engineer, you will have the opportunity to delve into the algorithms supporting the hardware. We are seeking an experienced engineer with exceptional programming skills and a genuine interest in ASIC verification. The verification environments at Sykatiya Technologies are complex, requiring individuals who can comprehend, implement, and maintain intricate software systems effectively. Preferred qualifications for this role include prior experience in hardware verification using SystemVerilog, UVM, low power verification, and formal methods. The ideal candidate is expected to be analytical, systematic, and detail-oriented in their approach. Join our team at Sykatiya Technologies and be a part of a dynamic environment where your skills and expertise in ASIC verification will be valued and nurtured.,
Build your career with Sykatiya Technologies, a company that values Technical Ability and the Attitude of its highly talented team. Our team consists of skilled engineers and experts from various domains such as Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are currently looking for candidates for the role of RTL/ IP Design with 3-12 years of experience to join our team in Bangalore. As an ideal candidate, you should have at least 5 years of experience in digital ASIC front-end design. You should possess a thorough understanding of design flows including RTL (VHDL, Verilog, and/or SystemVerilog). Experience with simulation tools like Questa or Xcelium and logic synthesis tools such as Synopsys DC is highly desirable. Candidates applying for this position should also have experience working with embedded microcontrollers and AMBA bus systems. A Bachelor's degree in science or engineering and proficiency in English communication are essential requirements for this role. If you are passionate about ASIC design and meet the above qualifications, we encourage you to apply and be a part of our dynamic team at Sykatiya Technologies.,
Build your career with Sykatiya Technologies. Sykatiya Technologies values Technical Ability and the positive Attitude of its highly talented team, which is evident in their contributions to customer projects. The team consists of skilled engineers and experts specializing in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are currently seeking an experienced IO Design professional with 3-8 years of experience to join our team in Bangalore. The ideal candidate should have a proven track record of leading a team in the development of at least one IO library from specification to GDS. In addition, the candidate should possess a strong understanding of all collateral views, their quality assurance, and be capable of reviewing collaterals effectively. The successful candidate will be responsible for guiding the layout team on design constraints and conducting layout reviews. Experience working on FinFET nodes and a solid understanding of reliability concepts such as Aging, HCI, BTI, and EOS are essential for this role. Proficiency in IO ring level considerations including supply sequencing, ESD, SSO/SSI, R-bus, supply-to-power pad ratio, and jitter analysis is also required. The candidate should have the ability to lead the project effectively, demonstrating strong leadership skills and technical expertise. If you are a motivated and experienced IO Design professional looking to take on new challenges and make a significant impact, we encourage you to apply for this exciting opportunity at Sykatiya Technologies.,
Role Summary: We are looking for a strategic and results-driven Business Development Manager/Director to lead initiatives that drive business growth and market expansion. The ideal candidate will be a seasoned relationship-builder and market explorer who can identify and pursue new business opportunities, nurture long-term partnerships, and lead the charge on revenue generation strategies. This is a high-impact role that requires a blend of strategic thinking, strong commercial acumen, and hands-on execution. Key Responsibilities: - Develop and implement strategic business development plans aligned with company goals. - Identify and evaluate new market opportunities, potential clients, and strategic partners. - Lead end-to-end partnership and deal lifecycle from prospecting and negotiation to closure and onboarding. - Build and maintain strong, long-lasting relationships with key clients, industry stakeholders, and decision-makers. - Collaborate cross-functionally with marketing, product, and operations teams to align business strategies. - Represent the company at industry events, conferences, and networking functions to enhance visibility and thought leadership. - Track market trends, customer needs, and competitive activity to inform business strategy. - Prepare and deliver business pitches, proposals, and performance reports for senior leadership. Qualifications & Experience: - Bachelors/ Master's degree in Business, Marketing, or related field; MBA is a plus. - 510 years of progressive experience in business development, sales, or strategic partnerships, preferably. - Proven track record of meeting/exceeding business development and revenue targets. - Strong negotiation, influencing, and presentation skills. - Ability to think critically, structure deals, and drive execution across multiple stakeholders. - Entrepreneurial mindset with a passion for growth and innovation.
Role & responsibilities About the Role: We are seeking an experienced and detail-oriented High-Speed Protocol Verification Engineer to join our growing team. The ideal candidate will have extensive hands-on experience in verification of high-speed interfaces such as PCI, PCIe, USB, Ethernet, MAC, and related protocols . You will work closely with architects and designers to ensure design correctness, coverage, and performance. Key Responsibilities: Develop and execute test plans for high-speed protocols such as PCI, PCIe (Gen1 to Gen5), USB (2.0/3.0), Ethernet (10/100/1G/10G), and MAC. Write and maintain SystemVerilog/UVM testbenches for functional verification. Collaborate with design teams to understand architecture and develop verification strategies. Debug RTL issues, analyze simulation failures, and provide comprehensive bug reports. Perform coverage analysis (code and functional) and drive coverage closure. Integrate VIPs (Verification IPs) and ensure compliance with industry standard protocol specifications. Work on assertions, checkers, and monitor development for protocol features. Participate in design and verification reviews, and contribute to continuous improvement. Preferred candidate profile Strong expertise in SystemVerilog, UVM methodologies. Solid understanding of PCIe, USB, Ethernet/MAC protocols . Experience in testbench architecture, test planning, and constrained-random verification . Knowledge of debugging tools like SimVision , Verdi , or similar. Exposure to protocol compliance testing and formal verification is a plus. Experience with scripting languages (Python, Perl, Tcl, Shell) for automation.
Role & responsibilities Key Responsibilities: Develop and execute test plans for high-speed protocols such as PCI, PCIe (Gen1 to Gen5), USB (2.0/3.0), Ethernet (10/100/1G/10G), and MAC. Write and maintain SystemVerilog/UVM testbenches for functional verification. Collaborate with design teams to understand architecture and develop verification strategies. Debug RTL issues, analyze simulation failures, and provide comprehensive bug reports. Perform coverage analysis (code and functional) and drive coverage closure. Integrate VIPs (Verification IPs) and ensure compliance with industry standard protocol specifications. Work on assertions, checkers, and monitor development for protocol features. Participate in design and verification reviews, and contribute to continuous improvement. Required Skills: Strong expertise in SystemVerilog, UVM methodologies. Solid understanding of PCIe, USB, Ethernet/MAC protocols . Experience in testbench architecture, test planning, and constrained-random verification . Knowledge of debugging tools like SimVision , Verdi , or similar. Exposure to protocol compliance testing and formal verification is a plus. Experience with scripting languages (Python, Perl, Tcl, Shell) for automation. Preferred candidate profile