Role & responsibilities Job Description- REQUIRED KNOWLEDGE, SKILLS, AND ABILITIES : • Work experience with node 7nm or lower node designs with advanced low power techniques is must. • Experience on ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, Physical Verification are essential part of the job. • Well versed with Cadence or Synopsys tools is important. • Experience with Static Timing Analysis in Primetime or Primetime-SI is important. • Hands-on experience in scripting languages such as PERL, TCL is important. • Timing closure on high-speed interfaces is a plus. • Knowledge on Full chip Physical Design is beneficial. • Good ASIC fundamentals and problem-solving skills is preferred. MANDATORY SKILLS: • Experience with 7nm node. • Experience with Cadence Innovus Preferred candidate profile

Job Summary: Participate in the feature design and early development of software from a QA standpoint, in order to understand and prevent bugs from being developed into the software from its inception. Duties/Responsibilities: Establish hybrid cloud testbeds to connect subnets between on-premise network and a VPC in AWS / Azure / GCP cloud platform. Design, develop and fix automated test scripts using Python or Go for the Aviatrix enterprise cloud defined network software. Ensure that GUI and APIs are functional in each release by designing, developing, and performing automated testing in Python to reduce repeated manual testing in the same areas and increase overall test coverage. Improve the CI/CD pipeline by stabilizing regression tests, triaging regression failures, and categorizing them into different buckets. Follow up with development teams to resolve the issue. Monitor performance numbers in each release and benchmark performance for different cloud platforms against other competitors using completed testing script. Build and use lab environments to simulate and debug customer networking configurations (e.g., routers, firewalls). Perform live troubleshooting, log analysis, and issue reproduction, for customer QA issues. Required Skills/Abilities: Demonstrate independent ability to solve problems. Frequent use and application of basic technical standards, principles, theories, concepts and techniques. Provide solutions to a variety of technical problems of moderate scope and complexity. Effectively write automated tests to cover code development. Excellent verbal and written communication skills. Excellent interpersonal skills. Python or Go Minimum Requirements: Education: Bachelors degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field. Experience: Two (2)+ years of experience in the job offered or in a software engineering-related occupation. Skills: Minimum two years of experience required in each of the following skills: networking protocols and cloud native architectures; software defined networking and cloud networking; debugging of Linux networking stack; performance benchmarking and system testing; platform and infrastructure development and testing with high-speed networking protocols; distributed computing; object-oriented Python; Go; Git version control to maintain large software codebases

Role & responsibilities Job Responsibility As the Lead, you will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, test cases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support. You will work very closely with the Architecture, RTL/uArch, and cross-functional teams. Areas of focus: Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with the RTL/uArch team. Job Requirements Experience with block level, cluster level or chip/SoC level verification. Should be a self-starter. Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog. Expertise in scripting languages, python or perl. Strong experience in helping emulation and validation. Experience with modeling various HW blocks, IPs for verification, emulation. Ability to analyze systems-level performance, profiling, and analysis. Post silicon support Preferred candidate profile

Role & responsibilities Roles & Responsibilities: Develop user-friendly interfaces and components for the Apps Portal using React.js / Angular / Node (project-specific). Ensure a seamless, intuitive, and consistent user experience across the platform. Collaborate with the backend team to integrate RESTful APIs and manage data flow. Create responsive layouts and ensure compatibility across devices and browsers. Maintain clean, scalable, and reusable code following industry best practices. Implement role-based access control and dynamic UI rendering based on user roles. Optimize performance and loading speed of the portal. Skills & Qualifications: Solid understanding of HTML5, CSS3, JavaScript (ES6+). Experience with React.js (preferred) or Angular / Node. Familiarity with responsive design, component-based architecture, and UI libraries like Material UI, TailwindCSS, or Bootstrap. Experience working with REST APIs and JSON data structures. Proficiency in Git, basic knowledge of CI/CD, and code collaboration tools. Good problem-solving skills and attention to UI/UX details. Good to Have (Optional): Knowledge of TypeScript and modern JS patterns. Experience with state management (e.g., Redux, Context API). Basic understanding of authentication flows (OAuth, JWT). Exposure to Agile methodology and working in a sprint-based environment. Preferred candidate profile

As an Analog Design Engineer at Sykatiya Technologies, you will be an integral part of our highly talented team that focuses on Technical Ability and a positive Attitude. Your contributions to projects will reflect our commitment to excellence for our customers. Our team consists of skilled engineers and experts in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are looking for an Analog Design Engineer with 3-12 years of experience to join our team in Bangalore. The ideal candidate will have experience in transceiver design for high-speed interfaces such as DDR, HBM, PCIe, USB3, and JESD204. Exposure to nodes below 22nm is a plus, along with experience in FINFET technology and the 32G-112G range of SERDES. In this role, you will be responsible for taking at least one block from circuit design to layout closure. You should also be able to guide the layout team in high-performance matched circuit design. Understanding reliability requirements such as ESD, EMIR, EOS, Aging, and being able to work independently while mentoring junior team members are essential qualities we are looking for. If you have exposure to post-silicon validation, it would be considered a plus. Join us at Sykatiya Technologies and be part of a dynamic team that values technical expertise, a positive attitude, and a commitment to excellence in Analog Design.,

Build your career with Sykatiya Technologies! Sykatiya Technologies values both technical ability and the attitude of its highly talented team, which is evident in their contributions to customer projects. The team consists of skilled engineers and experts specializing in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are currently looking for an Analog Design Engineer with 3-12 years of experience to join our team in Bangalore. The ideal candidate will have experience in transceiver design for high-speed interfaces such as DDR, HBM, PCIe, USB3, and JESD204. Exposure to nodes below 22nm is a plus, as well as experience in FINFET technology and the 32G-112G range of SERDES. The successful candidate should have taken at least one block from circuit design to layout closure and be capable of guiding the layout team for high-performance matched circuit design. Understanding reliability requirements such as ESD, EMIR, EOS, Aging, etc., is essential. The candidate should be able to work independently, mentor juniors, and have exposure to post-silicon validation. If you are a motivated Analog Design Engineer looking to work with a team of experts and contribute to cutting-edge projects, we encourage you to apply and be a part of our innovative team at Sykatiya Technologies.,