Lead Design Verification Engineer

Intel is seeking a highly technical Lead Design Verification Engineer for the Silicon Chassis team. In this senior technical leadership role, you will architect and deliver next-generation chassis IPs, designed to scale across multiple product families. You will establish verification strategy and methodology, drive technical development with deep expertise, and deliver first-pass silicon success through best-in-class IP design and verification practices. This role requires exceptional technical depth across advanced DV methodologies and tools, combined with strong expertise in interconnect protocols, cache coherency, memory architecture, and software integration. You will be a key technical authority, owning multiple high-impact IP blocks and setting standards for technical excellence.

Responsibilities

• Architect, develop, and deliver a comprehensive verification strategy and methodology that scales seamlessly from IP through subsystems to SoC-level verification
• Design and implement advanced verification environments, tools, and testplans enabling first-pass silicon success; develop sophisticated testbenches, checkers, VIPs, and complex behavioral models
• Collaborate closely with architecture, design, and software teams from initial product definition and specification reviews through implementation, bringup, and productization phases; balance complexity and ensure timely, high-quality execution
• Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics
• Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams
• Champion innovation across simulation, formal, and accelerated verification methodologies; develop and evaluate new ML-based flows and hybrid software frameworks
• Mentor and develop verification engineers; establish verification best practices and drive organizational technical excellence

Minimum Qualifications

• BS/MS in Electrical Engineering, Computer Science, or related field, with 14+ years of relevant experience in design verification; extensive background in IP DV with significant, demonstrated experience in subsystem and SoC-level verification
• Proven deep expertise in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; strong foundation in memory management (MMUs), cache coherency models and memory consistency implementation
• Demonstrated experience in verification of global functions including debug, trace, clock & power management, RAS, QoS, and security features
• Strong background in simulation-based verification methodologies including UVM, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools
• Advanced hands-on coding proficiency across SystemVerilog/UVM, software programming languages (C/C++), scripting (Python), and build systems; established track record of developing and delivering highly configurable and reusable verification collateral
• Demonstrated experience collaborating with formal verification and emulation teams to develop multimodal verification strategies
• Excellent communication and organizational skills with a proven track record of delivering on-time, high-quality silicon and establishing technical standards