165 Fpga Design Jobs - Page 4

FPGA Developer --> --> Location, Designation --> LocationRemote DesignationFPGA Developer Experience7- 9 Years Skills required: 1. Should have worked on USRP N310/X310 (N3xx/X3x0) 2. In-depth Knowledge of FPGA Architecture 3. Able to write own RTL custom HDL or drops in IP a) VHDL, Verilog, System,Verilog, Vivado HLS b) Xilinx IP, Vivado Block Diagram 4. Should have developed RFNoC Block 5. Have working knowledge of USRP Hardware Driver (UHD) 6. Able to write custom FPGA logic in RFNoC Blocks 7. Able to use library of existing RFNoC Blocks a) FFT, FIR, Signal Generator, Fosphor 8. Have understanding of GNU Radio interface to RFNoC Block 9. FPGA debugging and HW/SW integration 10. Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed 11. In-depth knowledge of XILINX ZYNQ 71xx/pl-kINTEX-7 based RFNoC architecture is must. 12.Understand Customer requirements, define architecture and detailed design 13. Good Customer Communication Skills 14. Working knowledge of Agile Feel Free To Contact Us...!!! Submit

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: FPGA Design Engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: 7 to 12 years of experience, mainly in design Experience in Verilog and/or SystemVerilog Working experience of AMD/Xilinx FPGA and Vivado Experience in Video domain (DisplayPort/MIPI) is preferred Candidate shall be working AMD Sattva site, Hyderabad. TekWissen Group is an equal opportunity employer supporting workforce diversity.

Job Title: FPGA Architect Location: Gurgoan, HR Experience: 10+ Years Job Summary: As FPGA Architect, you will lead the design development effort on a variety of projects in a highly collaborative, fast-paced environment. In this role, you will be responsible for the definition and development of complex FPGA designs for our Test products. You will work closely with RD Project Manager, Product Architects, Solution Teams, FPGA developers, Software Qualification and Software Engineers to develop new product offerings and improve existing ones. The candidate should be a strong team worker and should be able and willing to collaborate with other design teams located in US Europe. Qualifications Essential: Bachelor degree or masters degree in electrical / Electronic Engineering Minimum 10 years of RD experience in FPGA development (Altera, Xilinx) Experience of RTL languages - VHDL or Verilog Experience of Xilinx FPGA Tools Design Flow - Vivado, Chipscope, Quartus. Experience of EDA Functional Simulation tools Synopsys or Mentor or Cadence Experience of Altera or Xilinx FPGA Tools Design Flow Ability to quickly learn new technologies, protocols and product segments Experience of creating self-checking Simulation environment involving test bench, scripts for automation, writing test cases. Collaborate with system architects to define the system architecture and determine how the FPGA will interface with other components on the PCA board and choose an appropriate FPGA based on the projects requirements. Experience with timing closure for complex designs Excellent written skills which are required for creating documents like Product Definition, Detailed FPGA Design, Hardware Software Interface documents Self-motivated and self-organized Excellent team-player, responsive and accountable Excellent verbal communication skills Preferred: Experience with Keysight instruments like Oscilloscope, Analyzer, AWG BERT Experience of working on Protocols such as PCI Express, USB, MIPI (MPHY, DPHY, CPHY based), Ethernet, DDR etc. Experience in international collaboration (US EUR) Experience in multi-vendor collaboration (software supplied by and/or to external organizations)

Experienced in rtl design using verilog / system Verilog Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation Integration, rtl signoff tools, upf/low power signoff and cdc/rdc, lint Strong domain knowledge of clocking, system modes. Power management, debug, interconnect, safety, security and other architectures

3+Yrs Exp.Android device platform, Proficient In Kotlin Language knowledge of design patterns like MVP, MMVM, RxJava, and others knowledge of Android SDK, NDK, Android Studio, Gradle, and Lint Knowledge of Flutter or React native will be an advantage Required Candidate profile Candidate will be able to build and integrate android libraries and modules and design-build and maintain high performance reusable java and OOPS concept

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, weve got quite a lot to offer. How about you Position Overview Siemens EDA is looking for a highly motivated Product Engineer to help define, promote, and deploy hardware assisted acceleration with Veloce emulation and prototyping solutions at leading edge semiconductor and systems customers. As a hardware-assisted verification solutions expert you will be part of the world-wide Veloce experts team working with emulation and prototyping solutions for pre and post silicon validation, verification and software bring-up of industrys most complex SoC and FPGA designs using the latest advances in co-emulation technologies with Veloce Transactor Layer (VTL) transactors and testbenches. Key responsibilities Assist applications engineers (AEs) and customers with integration and debug of verification solutions to enable Testbench acceleration in a hardware-assisted verification environment Support PCIe, AMBA-based, UART, and serial protocol (SPI, I2C, ") transactors targeting emulation and prototype platforms. Build or support example designs for solutions that use SystemC or UVM transactors. Drive Veloce technology at various customers using hands-on technical expertise. Requires working directly with customers to ensure technical results are met. Promote technical customer service to build and improve customer relationships, ensuring long term customer happiness. Work closely with the sales team in a focused strategy to expand our business. Provide feedback and product ideas to our solutions product development teams. Troubleshoot and remove technical obstacles. Work very closely with all team member to ensure full customer happiness. Develop and deliver technical presentations/trainings on new features and product updates. Communicate customers' technical requirements to product marketing. Develop a network of technical relationships at a peer-to-peer level with our customers. Use complex design and tooling tasks involving multiple design environments. Cogently communicate software problems to product development. Assists other specialists in the design, development, and implementation of large-scale solutions on multiple software products and hardware platforms. Provides business and technical feedback to software and hardware vendors. Use advanced data exchange methodologies to facilitate effective data sharing between dissimilar systems or applications that span across engineering disciplines. Responsible for in-depth technical papers and presentations to customer management or at technical conferences. Guide junior engineers. Work with minimal direction on complex projects with latitude for independent judgment and discretion. Well skilled with broad proficiency. Required Qualifications We seek a graduate (Bachelor's) with 5+ years of related experience or post graduate (Master's) with 3+ years of proven track record. Familiarity with Verilog/SystemVerilog or SystemC and UVM Must have experience with emulation of large scale CPU, GPU or Systems-on-Chip (MPSoC) designs, emulation technologies, usages and industry approaches. Prior experience in a customer facing function such as application engineer from an emulation or prototype systems provider a plus! We've got a lot to offer, how about you A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! #LI-EDA #LI-HYBRID

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -12+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Skills Must have 1 position6+y, 1 position4+y Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash... Proficiency in Unix environment. Good communication skills Nice to have Bachelor's/Master's in ECE Other Languages EnglishB2 Upper Intermediate Seniority Regular

Job Description: Understand customers requirements /specifications /tender enquiry. Define DSP, System and Board architecture. Project ownership from concept to delivery. This includes identifying risks, dependencies, creating mitigation plan, tracking project schedule, discussions with customers, design reviews. Partition the algorithms for implementing in FPGA and/or in SW. Identify the building blocks & Signal Processing functions. Provide estimates on FPGA resources, computation bandwidth, and memory bandwidth. Create module level details from architecture, coding, simulation and perform peer reviews. Apply the methodologies for design, verification or validation. Define, create and maintain all project related documentation, especially design documents with detailed analysis reports. Provide support to customer during integration phases at test sites and support to production teams. Defining the architecture of RTL functions HDL Coding Simulation and Implementation Testing on board and debugging Professional Skills: VHDL Knowledge Xilinx tools for synthesis and implementation Thorough understanding of Xilinx FPGAs Functional Simulation Hardware Design : Logic Design & Debugging expertise FPGA Design : VHDL/Verilog RTL Coding, System C/ System Verilog FPGA Synthesis & PAR Tools Implementing DSP algorithms in FPGA environment for Radar and Electronic Warfare systems. Modeling the algorithms in Octave/MATLAB, generating test vectors, visualizing data. Working knowledge on interfacing with ADCs and DACs and interpreting their performance. Fluency, good communication & presentation skills. Configuration/Version control tools like SVN

Role Purpose The purpose of the role is to support process delivery by ensuring daily performance of the Production Specialists, resolve technical escalations and develop technical capability within the Production Specialists. Do Oversee and support process by reviewing daily transactions on performance parameters Review performance dashboard and the scores for the team Support the team in improving performance parameters by providing technical support and process guidance Record, track, and document all queries received, problem-solving steps taken and total successful and unsuccessful resolutions Ensure standard processes and procedures are followed to resolve all client queries Resolve client queries as per the SLAs defined in the contract Develop understanding of process/ product for the team members to facilitate better client interaction and troubleshooting Document and analyze call logs to spot most occurring trends to prevent future problems Identify red flags and escalate serious client issues to Team leader in cases of untimely resolution Ensure all product information and disclosures are given to clients before and after the call/email requests Avoids legal challenges by monitoring compliance with service agreements Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations as per SLA and quality requirements If unable to resolve the issues, timely escalate the issues to TA & SES Provide product support and resolution to clients by performing a question diagnosis while guiding users through step-by-step solutions Troubleshoot all client queries in a user-friendly, courteous and professional manner Offer alternative solutions to clients (where appropriate) with the objective of retaining customers and clients business Organize ideas and effectively communicate oral messages appropriate to listeners and situations Follow up and make scheduled call backs to customers to record feedback and ensure compliance to contract SLAs Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client Mentor and guide Production Specialists on improving technical knowledge Collate trainings to be conducted as triage to bridge the skill gaps identified through interviews with the Production Specialist Develop and conduct trainings (Triages) within products for production specialist as per target Inform client about the triages being conducted Undertake product trainings to stay current with product features, changes and updates Enroll in product specific and any other trainings per client requirements/recommendations Identify and document most common problems and recommend appropriate resolutions to the team Update job knowledge by participating in self learning opportunities and maintaining personal networks Deliver NoPerformance ParameterMeasure1ProcessNo. of cases resolved per day, compliance to process and quality standards, meeting process level SLAs, Pulse score, Customer feedback, NSAT/ ESAT2Team ManagementProductivity, efficiency, absenteeism3Capability developmentTriages completed, Technical Test performance Mandatory Skills: FPGA Design. Experience5-8 Years.

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: FPGA Design. Experience5-8 Years.

The ASIC Front-End Head is responsible for leading the front-end design team, ensuring high-quality Application-Specific Integrated Circuit (ASIC) designs, and driving innovation in digital chip development. This role requires expertise in RTL design, verification, synthesis, and architecture development, along with strong leadership and strategic planning skills. Key Responsibilities Technical LeadershipDefine and implement best practices for front-end ASIC design, ensuring efficiency and performance. Architecture & DesignOversee the development of digital circuits, including RTL coding, synthesis, and timing analysis. Verification & ValidationEnsure robust design verification methodologies using tools like UVM, SystemVerilog, and simulation frameworks. Cross-Team CollaborationWork closely with back-end design, physical design, and fabrication teams to optimize chip performance. Innovation & R&DStay updated with emerging semiconductor technologies and drive research initiatives. Mentorship & Team DevelopmentGuide and mentor engineers, fostering a culture of learning and technical excellence. Technical Project ManagementOversee front-end development timelines, ensuring timely delivery of high-quality designs. Required Qualifications EducationBachelor's or Master's degree in Electrical/Electronics Engineering, VLSI Design, or a related field. Experience15+ years in ASIC front-end design, with a proven track record of successful projects. Technical Skills: Expertise in HDLs (Verilog, VHDL), synthesis tools, timing analysis, and low-power design techniques. Leadership & CommunicationAbility to lead teams, manage projects, and communicate effectively with stakeholders. Problem-SolvingAnalytical mindset with a passion for optimizing digital designs for performance and efficiency. Reinvent your world.We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: ASIC Design. Experience5-8 Years.

DIGITAL & FPGA design engineer shall provide technical support in the domains of design and development, realizing & testing of signal conditioning, digital interfaces, control electronics, handling and implementation of signal processing and communication system design as well as implementing designs on FPGAs through automatic HDL code generation and verification techniques. Design Development digital designs/ FPGA programming to implement algorithms for image capture, data processing /analysis and data transmission in an embedded real-time control environment utilizing the latest FPGA technologies. Good understanding of digital, analog or radio frequency circuits, components, and subsystems Designs, knowledge of Performing preliminary and detailed analyses/simulations on Analog & Digital or mixed signal Interfaces. Responsibilities include specification generations, architecture/micro-architecture definition hands-on implementation work for every aspect of ASIC/FPGA design, working closely with the system engineers and ASIC/FPGA design implementations and verification. Delivery of expert level technical support in the resolution of FPGA application issues at all levels of realization of designs, The proactive aspects of the position will require participation in development projects, possibly as part of an international, cross organizational team and may include the generation of collateral and reference designs. Ownership of all aspects of the design verification of the FPGA chips and/or its functional blocks,design tools and its verification equipment. Should Support the design, development and testing, including upgrades, parts reliability requirements, failure analysis/corrective action investigations, special laboratory tests, performance evaluations, and design audits of in-house. Intend to work closely with FW and SW Engineers to test and verify electrical interfaces and protocols between the FPGA and embedded system devices Working knowledge in System Verilog/UVM environment platforms and be responsible for generating FPGA verification plan, verification matrix and coming up with verification environments for test and verification of flight FPGA code/modules. Relevant Bachelors or Masters Degree in Electronics Design, Embedded Electronics, Electronics & communication Engineering, Electrical Engineering.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. : Would be working on Qualcomm SoC System level Power and Performance in bare-metal validation environment. Develop comprehensive testplan for power and performance validation of the SoC both from a usecase requirement as well as design delta motivated. Determine Key Performance Indicator for the performance study by working closely with the respective IP teams in Design, DV and validation. Validation of System Low Power Modes, SoC shared rail power collapse validation Responsible for driving deep dive analysis on performance issues, bottlenecks and validating fixes or workarounds on subsystem and related SOC Modules. The ideal candidate would have a strong SoC architecture background along with good embedded system concepts on modern ARM/X86 based chipsets. Interface with subsystem validation, debug tools and SW teams during debugs. Develop low-level custom code on ARM and Hexagon Q6 processors using C/C++ and validate functionality and performance KPIs using debug trace dump Job : Bachelor's degree in Engineering, Computer Science, Electronics/Electrical Engineering or related field and 5+ years of full time experience ORMasters's degree in Engineering, Computer Science, Electronics/Electrical Engineering or related field and 3+ years of full time experience Familiar with CPU and SoC Architecture and micro-architecture, preferably ARM or ARM processor-based systems, clocking schemes, hierarchical memory systems, cache configurations and coherency issues in multi-core systems. Fundamental understanding of Static, Leakage and Dynamic power in a semiconductor design Experience with workload performance characterization, bandwidth and latency analysis, and driving microarchitecture investigations on CPU/GPU/Multimedia Systems with relevant performance metrics. Logical thinking and problem-solving ability with focus on performance centric validation Familiar with pre-silicon validation environments with Emulation and Virtual Bring-Up, etc. Basic statistics and data analysis skills to identify performance trends from large data sets and the technical bent to investigate anomalies (Good to have) Strong programming experience in at least one languageC,C++, Python (Must have) Good communication, English speaking/writing and team work attitude

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Function Camera Design Lead/Staff Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence. Skills/Experience 5-10 years with Masters (6 to 10 years with Bachelors) Solid experience in digital front end design for ASICsSolid Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domainsExpertise with various bus protocols like AHB, AXI and NOC designs Experience in low power design methodology and clock domain crossing designsUnderstanding of full RTL to GDS flow to interact with DFT and PD teams Experience in Tools like Spyglass Lint/CDC checks and waiver creationExperience in formal verification with Cadence LEC Experience in mobile Multimedia/Camera design is a plus DSP /ISP knowledge is a plus. Working knowledge of timing closure is a plusExpertise in Perl, TCL language is a plusExpertise in post-Si debug is a plus Good documentation skillsAbility to create unit level test plan General Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members. Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Knowledge of Analog and Digital Circuit Design, Verilog, System Verilog, VHDL, FPGA, CMOS. Hands on experience with Simulation and Verification, Timing and Power Analysis industry Standard Tools. Knowledge of Electronic Design Automation tools

In your new role you will:. Manage a Digital Verification Team working in R&D projects in a complex technical area. Resource pipeline balancing, allocate projects and co-ordinate the team. Building up and developing competencies and methodologies for IP/SoC Verification. Be the technical interface to internal development groups, project management and external development partners. Drive innovation in the form of new advancements (state-of-the-art verification methods, tool integration and flow automation). Envisage, implement, institutionalize and maintain the verification methods and infrastructure (e-g. automation to improve quality/efficiency in terms of cost and time). Accountable together with the PJM & CoC Head in meeting Quality, Cost, Deliverables, Represent your group in cross site methodology exchange. You are best equipped for this task if you have:. A degree in Electrical Engineering, Computer Science or similar technical field. At least 10 years of experience in the semiconductor industry inrelevant R&D departments and people management experience is must. Experience in Product Development, Digital Verification or Digital Design. Profound and proven problem-solving capabilities as well as strong communication skills to manage global and multi-cultural stakeholders and networks successfully. Good knowledge in your own technical area but a focus on management and coordination role. Excellent presentation skills which enable you to master the alignment across internal and external contacts in a multi-cultural environment. Highly motivated with ability to prioritize and perform under pressure. Proven ability to achieve results in a very dynamic and multi-site environment. Strong analytical and communication skills. #WeAreIn for driving decarbonization and digitalization, As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener, Are you in?. We are on a journey to create the best Infineon for everyone, This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills, Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process, Click here for more information about Diversity & Inclusion at Infineon, Show more Show less

Minimum qualifications:. Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.. 15 years of experience in ASIC RTL design.. Experience with RTL design using Verilog/System Verilog and microarchitecture.. Experience with ARM-based SoCs, interconnects and ASIC methodology.. Preferred qualifications:. Master’s degree in Electrical Engineering or Computer Engineering.. Experience driving multi-generational roadmap for IP development.. Experience leading interconnect IP design team for low power SoCs.. About The Job. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.. Responsibilities. Lead a team of people to deliver fabric interconnect design.. Develop and refine RTL design to aim power, performance, area, and timing goals.. Define details such as interface protocol, block diagram, data flow, pipelines, etc.. Oversee RTL development, debug functional/performance simulations.. Communicate and work with multi-disciplined and multi-site teams.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Job Description. As an FPGA Engineer specialised in RTL (Register Transfer Level) coding, you will be responsible for designing, optimising, and implementing hardware solutions on Field-Programmable Gate Arrays (FPGAs) to support high-frequency trading strategies. You will work closely with the trading systems team to develop and deploy ultra-low latency trading infrastructure, ensuring the highest levels of performance, reliability, and efficiency.. Key Responsibilities. RTL Design and Optimisation: Design and optimise FPGA-based solutions using RTL coding techniques to achieve ultra-low latency and high throughput for trading algorithms and strategies.. Algorithm Implementation: Implement trading algorithms and strategies in hardware, leveraging FPGA capabilities to minimise latency and maximise performance.. Hardware Acceleration: Identify opportunities for hardware acceleration of critical trading functions and develop FPGA-based solutions to achieve significant speedups.. Performance Analysis and Tuning: Conduct performance analysis of FPGA designs, identify bottlenecks, and fine-tune the implementations to achieve optimal performance.. Hardware Integration: Collaborate with software engineers and system architects to integrate FPGA-based solutions into the overall trading infrastructure, ensuring seamless operation and compatibility.. Testing and Validation: Develop test benches and perform thorough testing and validation of FPGA designs to ensure correctness, reliability, and robustness under real-world trading conditions.. Documentation and Reporting: Document FPGA designs, methodologies, and implementation details, and provide regular reports and updates to stakeholders on project progress and performance metrics.. Requirements. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.. Proven experience in FPGA design and development, with a focus on RTL coding using Verilog or VHDL.. Deep understanding of computer architecture, digital design principles, and hardware/software co-design concepts. Experience with high-frequency trading systems and ultra-low latency design techniques is highly desirable.. Proficiency in FPGA development tools and workflows, such as Xilinx Vivado or Intel Quartus.. Strong analytical and problem-solving skills, with the ability to optimise designs for performance, power, and resource utilisation.. Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced, team-oriented environment.. Show more Show less

We are seeking highy motivated individuas with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to hande the chaenging probems in future technoogies and designs. We are aso ooking for candidates with Strong C/C++background to ead our eading-edge agorithmswithin our EDA soutions to increase our design team’s productivity and chip quaity and performance. Our dynamic goba team is ooking to enist enthusiastic professionas to join word-cass hardware design teams responsibe for deveoping the most chaenging and compex systems in the word. We are seeking energetic, highy motivated individuas wiing to go the extra mie with the aim of heping the overa IBM deveopment team. Strong interpersona skis are needed to coordinate deiverabes and requirements from severa areas within and outside of the organization.There are many opportunities to gain and utiize a deep understanding of future issues and provide input towards decisions affecting system deveopment, ogica and physica design as we as sophisticated methodoogy directions. Individuas who are chosen to become a part of our word cass deveopment teams wi be heping advance IBM’s eadership in deveoping the highest performing computers and changing hardware soutions. Do you want to be an IBMerCome THINK with us! Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise 4+ years of IT experience Strong C/C++programming skis in a Unix/Linux environment is a must. VLSI knowedge, Knowedge in front end inting toos and checkers and RTL Checkers. Great scripting skis – Per / Python/She Proven probem-soving skis and the abiity to work in a team environment are a must Preferred technica and professiona experience RTL Lint Checkers , Front end verification fow, VLSI knowedge, VHDL/Veriog, computer architecture

Job Description As an FPGA Engineer specialised in RTL (Register Transfer Level) coding, you will be responsible for designing, optimising, and implementing hardware solutions on Field-Programmable Gate Arrays (FPGAs) to support high-frequency trading strategies You will work closely with the trading systems team to develop and deploy ultra-low latency trading infrastructure, ensuring the highest levels of performance, reliability, and efficiency, Key Responsibilities RTL Design and Optimisation: Design and optimise FPGA-based solutions using RTL coding techniques to achieve ultra-low latency and high throughput for trading algorithms and strategies, Algorithm Implementation: Implement trading algorithms and strategies in hardware, leveraging FPGA capabilities to minimise latency and maximise performance, Hardware Acceleration: Identify opportunities for hardware acceleration of critical trading functions and develop FPGA-based solutions to achieve significant speedups, Performance Analysis and Tuning: Conduct performance analysis of FPGA designs, identify bottlenecks, and fine-tune the implementations to achieve optimal performance, Hardware Integration: Collaborate with software engineers and system architects to integrate FPGA-based solutions into the overall trading infrastructure, ensuring seamless operation and compatibility, Testing and Validation: Develop test benches and perform thorough testing and validation of FPGA designs to ensure correctness, reliability, and robustness under real-world trading conditions, Documentation and Reporting: Document FPGA designs, methodologies, and implementation details, and provide regular reports and updates to stakeholders on project progress and performance metrics, Requirements Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, Proven experience in FPGA design and development, with a focus on RTL coding using Verilog or VHDL, Deep understanding of computer architecture, digital design principles, and hardware/software co-design concepts Experience with high-frequency trading systems and ultra-low latency design techniques is highly desirable, Proficiency in FPGA development tools and workflows, such as Xilinx Vivado or Intel Quartus, Strong analytical and problem-solving skills, with the ability to optimise designs for performance, power, and resource utilisation, Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced, team-oriented environment,

Position: Lead RTL Design Engineer (ASIC/FPGA) Location: Bangalore Experience: 7+ years Senior / Lead Level Role Overview Were seeking a proactive Lead RTL Engineer to define micro-architectures, implement robust RTL, guide integration, and collaborate across ASIC and FPGA domains. You will architect complex subsystems and mentor a high-performing team. Key Responsibilities Micro-architecture & Specifications: Create block-level design docs & detailed RTL micro-architecture for highcomplexity IP/subsystems. RTL Coding & Review: Develop clean, synthesizable RTL in Verilog/SystemVerilog/VHDL. Ensure code quality via lint/CDCC/static timing checks. Integration & IP Subsystems: Integrate with SoC/FPGA subsystems—protocols like AMBA/AXI, interconnects, memory, serial interfaces. Synthesis & Timing Closure: Lead flows using Design Compiler, Primetime, STA tools to meet timing and area goals. Verification & Debug: Coordinate with verification leads, support testbench development, and debug RTL—functional, wavebased, simulation. Leadership & Mentorship: Mentor engineers, lead reviews, steer integration, and liaise across RTL, verification, physical design, and architecture teams. Toolchain & Scripting: Script for automation (Tcl, Python, Perl, Shell); manage version control (e.g. Perforce, Git) . Innovation & Best Practices: Drive RTL design best practices, stay current with EDA tools, lowpower (UPF), CDC, linting, and continuous improvement. Required Qualifications Bachelor’s/Master’s in EE/CE or similar. 7+ years in RTL for ASIC/FPGA, +3 years in a leadership role. Expert in Verilog/SystemVerilog/VHDL, microarchitecture, FSMs, datapaths, CDC. Experienced with SoC/IP integration—AXI, AHB, APB, PCIe, USB, Ethernet, DDR, etc. Proficient with synthesis, STA, CDC, lint tools, DFT flows. Solid scripting with Tcl/Python/Perl/Shell and version control systems. Strong communication, documentation, team leadership, and cross-team collaboration skills. Preferred Skills FPGA prototyping and hardware bring-up expertise. Low-power methodologies (UPF, power gating). ASIC methodology experience (synthesis, timing, DFT, PPA closure). Familiarity with UVM verification, formal methods. Integration experience with high-speed or accelerator IP (NoC, memory controllers, etc.). What You’ll Get High-impact leadership in advanced RTL design for ASIC/FPGA cutting-edge chips. Opportunity to mentor and build a top-tier RTL team. Collaborative culture working with architecture, verification, PD, and system teams. Learning, ownership, and visibility across end-to-end chip delivery.

#Hiring FPGA Design Engineer Exp-5- 8Years Notice Period- 0 to 15Days Location- Bangalore Job Description: RTL and FPGA design, implementation, and timing closure using Xilinx & Synopsys development tools. Bring up and validate the design in the lab and generate test reports. Perform hardware validation tasks and debug IPs. Read, understand, and modify software drivers and scripts. Skills RTL Design & FPGA Implementation: Verilog, System Verilog, Vivado , ISE, Synplify, Design Compiler FPGA Platforms: Xilinx 7-series, Ultrascale/Ultrascale+, Zynq Toolchain Expertise: Xilinx Vivado, Synopsys DC/PT, ModelSim, VCS Hardware Validation: Bitstream generation, on-board debugging, performance tuning Lab Equipment: Oscilloscopes, logic/protocol analyzers, JTAG debuggers Software & Scripting: C, C++, Python, Perl, TCL, Bash Operating Systems: Linux (device driver understanding), embedded systems Interested candidates share your resume to sreeja.s@sasnee.com ,

Silicon Design Engineer (RTL Design and Development) Responsible for RTL design and development Experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools Perl, Python or TCL Scripting Email id- ta6@nipppondata.com