Senior Staff Engineer-STA

8 - 10 years

40 - 45 Lacs

Posted:1 week ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

  • In your new role you will:
  • Implement high-performance, low-power, and area-efficient digital designs.
  • Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis .
  • Optimize designs for power, performance, and area, and meet PPA goals.
  • Power analysis using PT-PX or equivalent flow.
  • Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs.
  • Define and evaluate constraints and signoff Test/DFT mode timing requirements.
  • Knowledge on Power analysis and PT-PX flow
Your Profile
You are best equipped for this task if you have:
  • Bachelors or Masters in Electrical/Electronics Engineering with 8+years of relevant experience.
  • Delivery oriented, Passionate to learn and explore, Transparent incommunication, Flexibility related to project situations.
  • Candidate should have strong Synthesis/STA fundamentals .
  • Has done timing sign-off including timing margin calculations independently, hands-on STA lead of projects .
  • Experience in handling STA of multi-power domain designs constraint mode merging.
  • STA flow development, abstraction with bottleneck identification.
  • Proficient in design margins and SDC constructs . TAT reduction in multi-mode, multi power domain/designs.
  • Generate timing ECOs for Physical design.
  • Drive ambitious schedules and enables dependent teams to accomplish.
  • Interface to design team and PD team and drive TAT reduction for PD.
  • Has experience in mentoring junior engineers.
  • Proficient with EDA tools from Synopsys/Cadence.
  • Excellent analytical communication skills.
  • Shown ability to collaborate in a multi-functional environment,cross-site or cross-time zone.
  • Proficient in Tcl and Perl or other scripting relevant language is a plus.

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