Principal Engineer Design

Develop and implement high-performance, low-power, area-efficientdigital designs for ASICs and SoCs using industry-standard EDA tools. Work closely with design teams to understand the requirements andconstraints of the design, and provide feedback on design feasibility,timing and power. Write and implement block level and top-levelconstraints for synthesis, perform timing closure and power analysis.Debug and resolve design issues related to synthesis, timing, power, andarea. Understanding of DFT flows, including scan insertion and ATPG.Optimize designs for power, performance, and area, and meet design goalswithin the given schedule. Implement pipelining at different levels forperformance optimization and timing closure. Perform power analysis andoptimize designs for low power. Proficient with EDA tools fromSynopsys/Cadence/Mentor. Excellent analytical & communication skills.Shown ability to collaborate in a multi-functional environment,cross-site or cross-time zone. Proficient in Tcl and Perl or otherscripting relevant language is a plus Your Profile Bachelors or Masters in Electrical/Electronics Engineering with 5+ yearsof relevant experience. In-depth knowledge of synthesis methodologies and tools from leading EDAvendors. Experience with writing design constraints for synthesis, timing closureand pipelining at different levels for performance optimization andtiming closure. Experience with power analysis and optimization flows such as powergating, clock gating, voltage scaling, and dynamic voltage frequencyscaling. Experience with scripting languages such as Perl, Python, or Tcl . Excellent problem-solving skills and ability to work independently andin a team environment. Strong communication and interpersonal skills, with the ability to interact effectively with cross-functional teams. Proven track record of delivering successful designs on time and meeting performance, power, and area goals.