FPGA Design Engineer

Job Title:

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About the Company

Our client is a leading technology-driven organization delivering cutting-edge solutions across semiconductor, telecom, and embedded systems domains. They work on next-generation hardware platforms, enabling innovation in high-speed, high-reliability FPGA-based designs. The company follows industry best practices, Agile methodologies, and provides opportunities to work on complex, real-world engineering challenges.

• Design, develop, and validate FPGA-based solutions for high-performance systems
• Work on complete FPGA design flow including RTL coding, synthesis, place & route, and timing closure
• Develop and review RTL using Verilog/SystemVerilog
• Perform RTL quality checks including Lint, CDC, and RDC analysis
• Define and validate timing constraints and perform STA
• Debug FPGA designs using inbuilt logic analyzers (ILA/SignalTap, etc.)
• Collaborate with cross-functional teams including validation, firmware, and system teams
• Review design documents and support FPGA validation activities
• Follow Agile development methodologies and version control practices

Mandatory Skills

FPGA design flow

RTL coding (Verilog/SystemVerilog)

CDC, STA, timing constraints

✔ FPGA debug experience using inbuilt logic analyzers

logic design

FPGA device architecture & clock structures

synthesis, Place & Route, and STA

bus protocols

slow-speed protocols

FPGA tools

✔ Basic scripting knowledge (Make, Perl, Shell, Python)

Git

Good to Have / Added Advantages

Telecommunication domain

PCIe, Ethernet IPs

error detection and correction techniques

Zynq design flow

➕ Experience working in Agile/Scrum teams

Important Note (Please Read Before Applying)

Do NOT apply if:

• You have

  less than 3 years or more than 6 years

  of FPGA design experience
• You do not have hands-on

  RTL & FPGA design flow experience

• Your notice period exceeds

  20 days

• Your background is unrelated to

  FPGA / RTL / Hardware design

Apply ONLY if you meet all mandatory skills and experience criteria.