FPGA Design Engineer

Role Overview: You will be working as an FPGA Engineer in Chennai with 37 years of experience, focusing on implementing high-speed interfaces, DSP, or control IPs to deliver timing-closed, production-grade cores for VPX/VME boards. Your role will involve close collaboration with hardware and firmware teams to integrate IP into full systems. Key Responsibilities: - Design, code, and simulate FPGA logic using VHDL/Verilog/SystemVerilog. - Integrate and validate IP cores such as PCIe, 10/40/100G Ethernet, and memory controllers. - Perform timing closure, floorplanning, constraint development, and optimization. - Develop testbenches, run simulations, and utilize lab hardware for hardware-in-loop verification. - Support board-level bring-up and debug activities using scopes, logic analyzers, and protocol analyzers. Qualifications Required: - Practical experience with Vivado or Quartus toolchains and bitstream flow. - Strong understanding of timing closure, CDC, constraints (XDC), and synthesis limitations. - Experience with PCIe and high-speed serial protocols. - Hands-on testbench/simulation experience with UVM familiarity being a plus. - Evidence of hardware integration and lab debug experience. Additional Details: Omit this section as no additional details about the company are provided in the job description. Role Overview: You will be working as an FPGA Engineer in Chennai with 37 years of experience, focusing on implementing high-speed interfaces, DSP, or control IPs to deliver timing-closed, production-grade cores for VPX/VME boards. Your role will involve close collaboration with hardware and firmware teams to integrate IP into full systems. Key Responsibilities: - Design, code, and simulate FPGA logic using VHDL/Verilog/SystemVerilog. - Integrate and validate IP cores such as PCIe, 10/40/100G Ethernet, and memory controllers. - Perform timing closure, floorplanning, constraint development, and optimization. - Develop testbenches, run simulations, and utilize lab hardware for hardware-in-loop verification. - Support board-level bring-up and debug activities using scopes, logic analyzers, and protocol analyzers. Qualifications Required: - Practical experience with Vivado or Quartus toolchains and bitstream flow. - Strong understanding of timing closure, CDC, constraints (XDC), and synthesis limitations. - Experience with PCIe and high-speed serial protocols. - Hands-on testbench/simulation experience with UVM familiarity being a plus. - Evidence of hardware integration and lab debug experience. Additional Details: Omit this section as no additional details about the company are provided in the job description.