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STMicroelectronics
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Digital Verification Engineer

Digital Verification Engineer

STMicroelectronics

0 years

0 Lacs

sadar uttar pradesh india

Posted:2 days ago| Platform:

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Skills Required

verification power technology drive collaboration development test simulation debugging cutting planning architecture analysis code simulations testing vhdl verilog communication graphics networking ethernet usb vision radar scripting perl python unix regression management

Work Mode

On-site

Job Type

Full Time

Job Description

OUR STORY

At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today.When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world!Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential.Drive to “zero-defect”. Responsibilities encompass the development of verification test bench, development of verification components, test case development for simulation, debugging failures and creating simulation cases for various studies. As an experienced professional, work with the cutting-edge verification methodologies on standalone IPs, Subsystem level and SoC level.

Responsibilities Include But Not Limited

Lead and manage complete SoC level Verification activities
Verification planning, reviewing, architecture definition, Verification test bench development and implementation
Development of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs.
Development of direct and constrained-random stimulus; Understanding and analysis of RTL code, functional, assertion coverage results;
Strong skills in debug, failure re-creation and root cause analysis
Gate level simulations (unit delay, and with SDF annotated) and its debugging
Test pattern debugging and testing for verification and automatic testers
Continuous improvement of verification methods/tools/flows/processes together with EDA partners. Finding cost effective and innovative verification techniques
Low Power intent verification using CPF, UPF will be desirable.
Assertion based verification will be a plus

Technical Background/Key Skills

Qualification: Bachelors/Masters in Electronics/Computer Science
VHDL/Verilog, System Verilog, C language
OVM/UVM, Class based verification methodologies
Deep Understanding of multi core based SoC architecture
AMBA – AXI, AHB, APB bus protocols
NIC/FlexNOC interconnect with Cache coherency, DDR3/LPDDR4/Flash memory subsystem architecture knowledge
Communication Protocols like CAN, Graphics/Multimedia/Networking IPs like PCIe, MIPI, GPU, Ethernet, USB, DSP, Image/Computer Vision, RADAR processing
Scripting proficiency - PERL, Python, UNIX/LINUX
Simulation tools like – Xcelium/VCS/Questasim. Planning and regression tools like VManager
Exposure to any of defect and version management tool

Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future!
To discover more, visit st.com/careers

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Digital Verification Engineer