We are developing state-of-the-art SoCs from architecture to final product involving automotive centric design methodologies and flows tailored for functional safety. We have a presence across multiple geographies and are currently in search of a Principal level IP/SoC Design Verification Engineer. RESPONSIBILITIES Develop testbenches using System Verilog and UVM for functional and power aware RTL Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage. Develop test plan, UVM based test sequences, layered sequences, virtual sequencers Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware and Gate level timing simulation. Develop C testcases for HW-FW simulation and FPGA prototyping Provide regression setup, debug of RTL and gate level netlist Review industry standard spec and augment test plan to improve quality of verification Participate in post silicon bring up, validation and compliance testing and debug Work collaboratively with cross-functional teams like ASIC Architect, ASIC Designers, firmware development team to ensure successful delivery of product MINIMUM QUALIFICATIONS Proven track record of verification, taking several chips from specification to tape out Proven expertise with UVM and/or System Verilog based verification Excellent understanding of ASIC verification methodologies and proven experience of verification Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, and Jira. Experience with SoC interfaces, embedded processors, networking protocols, security protocols and video formats will be a big plus. Strong written and verbal communication skills and ability to work independently. Bachelors in Electrical Engineering or equivalent and 5+ years of experience

Job Description Summary We are developing state-of-the-art SoCs from architecture to final product involving automotive centric design methodologies and flows tailored for functional safety. We have a presence across multiple geographies and are currently in search of a Principal level IP/SoC Design Verification Engineer. RESPONSIBILITIES Develop testbenches using System Verilog and UVM for functional and power aware RTL Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage. Develop test plan, UVM based test sequences, layered sequences, virtual sequencers Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware and Gate level timing simulation. Develop C testcases for HW-FW simulation and FPGA prototyping Provide regression setup, debug of RTL and gate level netlist Review industry standard spec and augment test plan to improve quality of verification Participate in post silicon bring up, validation and compliance testing and debug Work collaboratively with cross-functional teams like ASIC Architect, ASIC Designers, firmware development team to ensure successful delivery of product MINIMUM QUALIFICATIONS Proven track record of verification, taking several chips from specification to tape out Proven expertise with UVM and/or System Verilog based verification Excellent understanding of ASIC verification methodologies and proven experience of verification Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, and Jira. Experience with SoC interfaces, embedded processors, networking protocols, security protocols and video formats will be a big plus. Strong written and verbal communication skills and ability to work independently. Bachelors in Electrical Engineering or equivalent and 5+ years of experience

Job Description Summary We are looking for an expert AMS Verification Engineer that is familiar with the complete flow/methodology and can establish a modern AMS verification environment in a high-paced start-up. Responsibilities Review existing company designs and understand communication standards Establish a state-of-the-art AMS verification environment Co-develop an AMS verification plan with DSP/Digital/Analog teams from chip specification Execute plan and debug issues with team Develop test benches and models Provide feedback to design teams for AMS netlist optimization Expand and monitor AMS verification coverage and drive schedule timeliness Assist with debug simulations for silicon bring-up as necessary Create reports and documentation of AMS verification results and coverage Minimum Qualifications PhD/MSEE with at least 5 years domain expertise and have prior circuit design experience Proven record of AMS verification for mixed-signal SOCs in example fields such as: Ethernet/PCIe/MIPI DSL/DOCSIS 11, GSM/LTE Ethernet/PCIe/MIPI DSL/DOCSIS 11, GSM/LTE Expert at one of Cadence AMS-D/Incisive/Xcelium, Mentor Symphony, Synopsys VCS-AMS Able to model analog circuits in Verilog / Verilog-A / Verilog-AMS / SystemVerilog and adept with simulations in Explorer/Assembler Experience in solving Analog-Digital tool interaction issues and simulation slowness Experience in solving Analog-Digital tool interaction issues and simulation slowness Good written and verbal communication skills Additional experience in the following preferred: PERL, Python UVM, UPF Analog timing verification and .LIB generation DSP based data communication systems design ISO 26262 FuSa certification (SC-AFSP)