1672 Dft Jobs - Page 3

About the Role — PCB Design Engineer Location: Gurugram Experience: 5–10 Years Qualification: B.Tech/B.E. in Electrical/Electronics/ECE or related discipline (Mandatory) Who We Are: At Boon , we’re building cutting-edge water tech solutions to make clean drinking water more sustainable, efficient, and accessible. As part of our Power Electronics team, you’ll help us develop high-performance hardware that powers next-generation water purification and distribution systems deployed globally. Role Overview: We’re looking for an experienced PCB Design Engineer with deep expertise in designing robust, high-reliability PCBs for power electronics applications. You’ll work extensively with Altium and other tools , apply EMI/EMC best practices, and handle thermal-critical layouts for power-dense systems. Key Responsibilities: Design complex, multi-layer PCBs for power electronics including DC-DC converters, inverters, SMPS, and motor drives. Develop and maintain schematic diagrams, PCB layouts, footprints, and libraries in Altium Designer. Optimize PCB layouts for signal integrity, power integrity, thermal performance, and high-current handling. Ensure compliance with EMI/EMC standards and integrate grounding, shielding, and filtering best practices. Perform DRC/ERC checks and support DFM/DFT processes for manufacturability and testability. Collaborate cross-functionally with electrical, mechanical, and firmware engineers throughout product development. Integrate 3D component models and conduct mechanical fit and clearance checks using Altium’s 3D design capabilities. Coordinate with PCB fabrication and assembly vendors for prototyping and production runs. Support prototype bring-up, debugging, and validation with the testing team. Manage documentation including Gerber files, BOMs, assembly drawings, and design revisions. What You’ll Need: Bachelor’s degree in Electronics/Electrical Engineering or a related field. 7–10 years of hands-on PCB design experience, ideally in power electronics. Advanced proficiency with Altium Designer (schematic, layout, 3D, library management). Strong understanding of EMI/EMC principles and practical implementation. Experience designing for high-voltage, high-current, and thermally demanding applications. Competency in 3D modeling and mechanical integration of PCB assemblies. Solid grasp of IPC standards and PCB manufacturing processes. Excellent analytical, problem-solving, and debugging skills. Strong communication and teamwork abilities. Join us at Boon and help shape innovative hardware that makes clean water more sustainable for millions.

Company Description Pronesis partners with leading technology companies globally to offer world-class solutions. The company specializes in a variety of engineering services including ASIC/VLSI design, embedded product development, and product engineering. Whether it’s SoC verification, hardware design and testing, or product support, Pronesis ensures top-tier service in every domain. What You’ll Be Doing: Lead block/chip level Physical Design (PD) activities , including floor planning, abstract view generation, RC extraction, PNR, STA, EM/IR drop, DRCs, and schematic-to-layout verification. Collaborate with RTL/design teams to solve complex design challenges and optimize PPA . Debug tool/design issues and improve RTL2GDSII flows for better efficiency. Handle full-cycle PD tasks for GPU and other ASICs. Drive block-level and full-chip floor-planning, timing closure, and physical verification . Collaborate with RTL design, verification, and DFT teams to ensure high design quality and robustness. Develop and implement physical design methodologies and best practices to enhance design efficiency and quality. What We’re Looking For: BE/BTech/MTech in Electronics/Electrical Engineering or equivalent experience. 4–8 years of experience in Physical Design. Strong understanding of RTL2GDSII flow, synthesis, place & route, CTS, STA, timing convergence, and layout closure . Hands-on experience with Cadence Innovus, Synopsys ICC2/PrimeTime/Tempus or equivalent PD tools. Expertise in high-frequency design methodologies and advanced technology nodes up to 2nm . Proficient in Perl, Tcl, Python, and tool-specific scripting for automation. Knowledge of Verilog/VHDL and digital logic design. Strong analytical, problem-solving, and communication skills with the ability to work in a global, collaborative environment. Locations: Ahmedabad & Bangalore.

Company Description SmartSoC Solutions is a leading Product Engineering Services company specializing in Semiconductor Design Services, Embedded Systems, Digital Solutions, Artificial Intelligence, Machine Learning, IoT, Networking, and Robotics. We cater to diverse industries, including Semiconductor, Consumer Electronics, Telecom & Data Networking, Industrial, Automotive, and Agriculture. Our mission is to empower clients to design and build next-generation products, offering comprehensive services from design to production. With a global presence and a talented team of over 1,250 scientists and engineers, we are dedicated to driving success around the world. Role Description This is a full-time, on-site role located in Hyderabad for a DFT (Design for Testability) Lead at SmartSoC Solutions. The DFT Lead will be responsible for developing and implementing DFT architecture, creating and validating test plans, and working closely with design and verification teams to ensure testability. Day-to-day tasks include implementing scan insertion, MBIST, boundary scan, and ATPG, as well as analyzing test coverage and working with clients to address technical issues and provide solutions. Qualifications Strong Analytical Skills and problem-solving abilities Excellent Communication skills for interacting with teams and clients Experience in Consulting and providing technical solutions Strong Customer Service and Sales skills Proficiency in DFT methodologies and tools Familiarity with semiconductor design and testing processes Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field Experience in the semiconductor industry is a plus

Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff include formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. BS/BTech degree with 8 years of experience, or MS/MTech degree with 6 years of experience, in Electronics Computer Engineering, or a related field. Preferred qualifications include at least 7-13 years of experience in physical design using industry EDA tools and proficiency in Python/Perl/TCL programming languages. This role falls under Experienced Hire category and will have Shift 1 (India) as the primary location. The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. The SIG business group brings together experts with diverse backgrounds, cultures, and experiences to deliver innovative computing experiences. Please note that this role will require an on-site presence. Job posting details such as work model, location, or time type are subject to change.,

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff include formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications BS/BTech degree with 8 years of experience, or MS/MTech degree with 6 years of experience, in Electronics Computer Engineering, or a related field. Preferred Qualifications: At least 7-13 years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intels leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. Show more Show less

Job Title: Computational Chemist Function: Science & Technology Reports to: Research Scientist Scope: PC Location: Unilever R&D Bangalore About Unilever Established over 100 years ago, we are one of the world’s largest consumer goods companies. We are known for our great brands and our belief that doing business the right way drives superior performance. We believe that the winning businesses of tomorrow will be those which anticipate and respond to the huge changes shaping people’s lives across the world. We are more certain than ever that it is the right time to focus our sustainability efforts on the four key priorities where we are best placed to drive impact: climate , nature , plastics and livelihoods . Business Context And Main Purpose Of The Job Personal Care (PC) business is focused on being the best in class company for Personal care products with personalised desirable experiences and beauty solutions for whole-body wellness. The business is committed to address (a) Big Unmet consumer need/insight/idea (b) Right to WIN with superior proposition with product love & noticeable superiority (c). clean beauty product with reduce environmental footprint. The role of the Science and Technology (S&T-PC-Physical science) pillar within R&D is to deliver breakthrough “Differentiated Technologies, with capabilities” to meet PC goals around the world. S&T-PC-Physical science team is focused on building future fit skills team and talent in “Advanced Materials, Measurements delivering long lasting freshness for whole body & personalisation Integrated with Digital”. S&T-PC-Physical science team is employing advanced materials & measurements science for superior multi targeted consumer needs with perceivable efficacy and care across deodorant and skin cleansing category. The teams focus is to deliver faster and cost-effective Innovations through Advanced Material Pillar leveraging “Computational chemistry”. The purpose is to build differentiated innovation roadmap & impactful claims by (a) Developing and applying QSAR models to predict properties like ADMET, binding affinity, or material properties based on molecular descriptors. (b). Performing Density Functional Theory (DFT) and other QM methods to investigate molecular structure. To meet our purpose, we need candidate with expertise in materials design, development, and analytics using digital approach. Main Accountabilities Collaborate with scientists to conduct modelling and simulation projects, presenting results and insights to stakeholders. Adopt AI/ML and deep learning algorithms to develop and test hypotheses relevant to material science. Perform laboratory experiments to validate hypotheses and support simulation results. Streamline modelling workflows to facilitate the adoption of digital tools, enabling quicker insight generation and decision-making. Maintain and expand expertise in materials modelling and simulation by staying updated with the latest research and technological advancements. Enhance team's capabilities in materials design, development, and analytics using digital approach. Support in managing external research programs and data-driven initiatives to advance material science research. Key Interfaces Senior Line manager S&T Programme team S&T Category Discover Leaders Patent attorney Key Skills B.Tech/M.Tech in Chemical Engineering or master’s degree in chemistry / physics / Material Science Specialization in modelling, simulation and ML or minimum 3 years’ experience in modelling and simulation. Strong background in quantum mechanics, molecular modeling, and statistical analysis. Relevant Experience Experience in QSAR modeling, quantum mechanics & DFT. Ability to work multi-functional teams. Experience in experimental research preferably in materials science or a related field. Standard Of Leadership Purpose & Service Personal Mastery Agility Our commitment to Equality, Diversity & Inclusion Unilever embraces diversity and encourages applicants from all walks of life! This means giving full and fair consideration to all applicants and continuing development of all employees regardless of age, disability, gender reassignment, race, religion or belief, sex, sexual orientation, marriage and civil partnership, and pregnancy and maternity. "All official offers from Unilever are issued only via our Applicant Tracking System (ATS). Offers from individuals or unofficial sources may be fraudulent—please verify before proceeding."

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Masters degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum of 5+ years experience in the area of ASIC/DFT -In depth knowledge of DFT concepts -In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors -Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax) -Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem solving skills -Excellent communication and team work skills and good English is required

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Responsibilities Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 3+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.),synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globeand possess good communication skills.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8+ years experience in the area of ASIC/DFT -In depth knowledge of DFT concepts -In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors -Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax) -Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem solving skills -Excellent communication and team work skills and good English is required

General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. Qualcomm CDMA Technologies (QCT) is a global leader in Multimedia integrated circuits (ICs), software and systems for wireless consumer devices including Smartphones, Netbooks and E-readers. Our teams are developing advanced technologies to enhance mobile devices in areas including 2D and 3D graphics, audio/video, display and architecture. These Multimedia ASICS are co-designed with our Modems, Applications Processors, Analog Codecs and Power Management ICs to deliver highly-integrated, high-performance and low-cost chipsets to our customers and partners. You will be implementing the industry's leading edge graphics processor, specific areas include 2D and 3D graphics, streaming processor, high speed IO interface and bus protocols. In this position, the designer will be responsible for architecture and micro-architecture design of the ASIC, RTL design and synthesis, logic and timing verification. The successful candidate for this position will specify and design digital blocks in our Multimedia Graphics team that will be integrated into a broad range of devices. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field Previous experience in designing GPU or CPU cores and ASICs for Multimedia and Graphics applications in deep sub-micron CMOS processes for volume productionExperience with Verilog/VHDL design, Synopsys synthesis, static timing analysis, formal verification, low power design, test plan development, coverage-based design verification, and/or design-for-test (DFT)Experience with Computer Architecture, Computer Arithmetic, C/C++ programming languages is desiredExposure to DX9~12 level graphics HW development is big plusGood communication skill and desire to work as a team player Required: Bachelor's degree in Computer Science, Electrical Engineering, Information Systems, or related field.Preferred: Master's degree in Computer Science, Electrical Engineering, Information Systems, or related field. ASIC, hardware, design, GPU, OpenGL, DirectX, RTL, Verilog, SystemVerilog Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Experience: 5+ years Key Responsibilities: · Own and drive floorplanning for complex SoC or IP blocks from RTL to GDSII. · Collaborate with RTL, DFT, and architecture teams to understand design requirements and translate them into optimal floorplans. · Perform macro placement , power grid planning , pin placement , and block-level partitioning . · Analyze and optimize for congestion , timing , area , and power . · Work closely with place & route , clock tree synthesis , and timing closure teams to ensure floorplan quality. Required Skills: Strong hands-on experience with EDA tools like Cadence Innovus, Synopsys ICC2, or Mentor Olympus. · Deep understanding of physical design flow , especially floorplanning, placement, and routing. · Experience in hierarchical design , multi-voltage domains , and power planning . · Good knowledge of timing analysis , signal integrity , and DFT-aware floorplanning . Proficiency in scripting (Tcl, Perl, Python) for automation and debugging.

Job Description: We are looking for DFT Engineers with 3+ years of experience in Scan, MBIST, and ATPG. The role involves developing and implementing advanced DFT methodologies to ensure testability and high-quality silicon. Key Responsibilities: Hands-on experience with Scan insertion and Scan DRC/Coverage debug. Strong background in ATPG pattern generation and fault coverage analysis. Expertise in Gate-level simulations (Zero delay / Timing delay simulations). Worked on JTAG protocols. Experience in MBIST insertion, verification, and debug. Proficiency in Perl/Tcl scripting for automation of flows. Familiarity with timing verification, formal verification, and PD flow (a plus). Ability to debug and optimize DFT implementation for quality silicon.

Hiring DFT Engineers (412 yrs) for full-chip ATPG, MBIST, silicon debug & ATE delivery. Skills: TestKompress, ETVerify, VCS, Perl/Shell. Locations: Bangalore, Hyderabad, Cochin, Pune. Join a global ASIC design team driving quality silicon!

Job Description Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression. Implementing, integrating and verifying memory BIST and boundary scan. ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow. Cross functional teams interaction for issue resolution. Participate in driving new DFT methodology and solutions to improve quality, reliability and insystem test and debug capability. Hiring candidate with these specific personal characteristic and qualifications. Mentoring junior engineers and drive innovation/automation. Excellent in problem solving and analytical skills. Excellent communication, team work and networking skills. Primary Skills Should Have Good understanding of Design and DFT Architecture. Should have been part of atlest 3 Tapeout SoC. Well Versed with ATPG Tools & MBIST Tools. Secondary Skills Team Player, Strong Business Acumen with understanding of organizational issues (conflict resolution between stakeholders). Familiarity with Desired Flexibility and adaptability with respect to project management

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Overview: This position centers onfloor-planning expertise at both block and top levelsfor industry-leadingCPU core designs, with a strong emphasis on scalability and achieving aggressivePower, Performance, and Area (PPA)targets. The role involves working oncutting-edge technology nodesand applyingadvanced physical design techniquesto push the boundaries of CPU performance and efficiency. Preferred Qualifications: Masters degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience In depth end to end experience from RTL2GDS, taping out at least 5 complex designs Direct hands-on experience with bus/pin/repeater planning for entire IP Key responsibilities include: Drivingfloorplan architecture and optimizationin collaboration with PD/RTL teams to maximize PPA Engaging incross-functional collaborationwith Physical design, timing, power, and packaging teams to ensure holistic design convergence Partnering withEDA tool vendorsand internal CAD teams to develop and enhanceautomation flows and methodologiesfor improved design efficiency Makingstrategic trade-offsin design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets End to End Physical verification closure for subsystem. The ideal candidate will have/demonstrate the following: Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler. Must have good knowledge of static timing analysis, reliability, and power analysis Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance Solid working knowledge of scripting skills including tcl, perl or python Excellent communication skills and collaborating in a team environment is a must Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Experience in IO, Bump planning and RDL routing Strategy. Preferred Skills: Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and Area Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous Hands on experience on Innovus/FC tool based scripting & python/TCL scripting. Prior experience in flow and methodology development is an advantage Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams Minimum Qualifications: Bachelors degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level Strong background in VLSI design, physical implementation and scripting Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools Hands on experience taping out designs in sub-micron technology node design less than 10nm Expect strong self-motivation and time management skills

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum of 7+ years experience in the area of ASIC/DFT -In depth knowledge of DFT concepts -In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors -Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax) -Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem solving skills -Excellent communication and team work skills and good English is required

General Summary: Minimum 4 to 6 years of work experience in ASIC RTL Design. Strong expertise in MBIST insertion, Scan insertion, and ATPG. Proficiency with SMS MBIST insertion tool is mandatory. Must have hands-on experience with handling sub systems with multiple memory types and grouping. Additional experience in memory redundancy, BIRA analysis, and repair solutions is highly desirable. Solid understanding of multi-memory bus interfaces and functional safety BIST requirements is a strong advantage. Exposure to Automotive System Designs, Memory Controller Designs, and Microprocessors is a plus. Experience in low power design and synthesis/timing concepts for ASICs is preferred Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 8+ years of Hardware Engineering or related work experience. 2+ years of experience with circuit design (e.g., digital, analog, RF). 2+ years of experience utilizing schematic capture and circuit simulation software. 2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 1+ year in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products. Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues. Writes detailed technical documentation for complex Hardware projects. Level of Responsibility: Works independently with minimal supervision. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities/job duties Memory Frontend Model development/verification/delivery/debug/Automation Memory Front End team introduction: At Qualcomm memory team, we specialize in front-end modeling for a wide range of memory IPs. This includes various architectures such as single-port memories, pseudo dual-port designs, register files, CPU memories, and complex custom memories developed from the ground up. Each IP development undergoes comprehensive verificationcovering functional, formal, BIRA, and DFT domainsand is rigorously validated through an extensive QA suite to ensure alignment with the actual memory circuit implementation Qualifications Masters in Electronics and communication Engineering or Electrical Engineering or related field with 0-2 years experience. In this position candidate will be part of memory FrontEnd modelling team where he/she will be responsible for below: Design and implement behavioral models in Verilog/System Verilog for compiler-generated and custom memory components. Maintain and enhance memory compilers to ensure accurate generation of behavioral Verilog models. Develop and support LVLIB and MASIS models for memory BIST (Built-In Self-Test) applications. Create FPGA-compatible models tailored for emulation platforms. Build DFT (Design-for-Test) and Fast Scan models to support comprehensive test coverage. Execute signoff simulations for both functional and formal verification across all compiler and custom memory models. Run comprehensive QA suites to validate that all memory models accurately reflect the intended circuit implementations. Develop and maintain signoff verification tools and QA automation frameworks for memory model validation. Conduct post-release QA checks to ensure model quality and reliability. Manage customer releases , ensuring readiness and documentation. Provide support to SoC teams , assisting with debugging and resolving memory interface issues related to the models. In this position, candidates should have below understating and hands on experience: Strong understanding of memory architecture and functionality. Solid grasp of CMOS low-power circuit design principles. Proficient in simulation tools such as Vsim, VCS, Finesim, and CustomSim. Deep expertise in Verilog and System Verilog coding practices. Familiarity with BIST modeling frameworks like LVLIB and MASIS. Good working knowledge of CLP and Static Timing Analysis (STA). Experience with Unix, Shell scripting, Perl, and Python is a plus. Excellent communication and collaboration skills.

General Summary: Job Function : Camera Design Lead/Staff Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence. Skills/Experience 5-10 years with Masters (6 to 10 years with Bachelors) Solid experience in digital front end design for ASICsSolid Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domainsExpertise with various bus protocols like AHB, AXI and NOC designs Experience in low power design methodology and clock domain crossing designsUnderstanding of full RTL to GDS flow to interact with DFT and PD teams Experience in Tools like Spyglass Lint/CDC checks and waiver creationExperience in formal verification with Cadence LEC Experience in mobile Multimedia/Camera design is a plus DSP /ISP knowledge is a plus. Working knowledge of timing closure is a plusExpertise in Perl, TCL language is a plusExpertise in post-Si debug is a plus Good documentation skillsAbility to create unit level test plan General Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members. Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision Responsibilities Digital design and development (RTL) working in close collaboration with Multi-site leadsDeveloping the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoCDesign and implement defined tasks independently. Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ years of experience in physical design is mandatory for this position Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc.

The Brushed and Stepper (BSM) Motor drives business product line is part of Motor Drive products group in ASC.BSM products are a key focus area for R&D and product development for TI. Precise Signal, Intelligent Control algorithms and Power transfer are key areas of research and product development for the team. We are looking for experienced, highly driven, fast-learner candidates to join their IC Design & Verification team based in Bangalore, IN. We develop cutting edge, highly differentiated parts across Industrial & Automotive motor drives market. This team has full product development responsibility from definition till releasing product to market. We also take pride in challenging norms on innovation & executing those innovative ideas into products with aggressive, customer-driven timelines. What can you expect to learn in this role? (Opportunity) Close interaction with Systems Team on customer requirements and use cases Working closely with analog design to understand chip level requirements and implementation Drive DV and test methods for validation/verification of the device Understand various DC motor drive systems, key care bouts and development flow Post-Si debug What will you be doing in this role? (Responsibilities) As AMS DV Engineer for a project/s you are expected to: Develop and execute detailed pre-silicon Verification plans working closely with Systems and Applications team and Analog and Digital design teams Develop chip-level test-cases and behavioural models for analog blocks based on the verification plan Run an automated / regression based DV suite and extract key measurements based on automatic extractors and populate them on Starfish Work closely with design and systems teams to review / close spec gaps and design bugs, as they arise Implement AMS TBs in Verilog-AMS and / or Cadence Virtuoso to apply stimulus and check for pass/fail criteria Drive new and improved methodologies where needed, work with the EDA team to upgrade DV tools and flows Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tape-out Participate in design reviews and create necessary design verification and product documentation Work with test engineers / designers to come up with optimized DFT techniques and execute pre-silicon verification of mixed-signal products To mentor junior engineers and interns. Required Qualifications: Knowledge and Skills Good grasp of analog design and digital design fundamentals and be able to apply this knowledge to the full chip verification of a mixed signal IC Understanding of basic analog building blocks and mixed signal blocks. Strong hands-on working experience in Analog / digital verification for Mixed-signal chips Ability to write an exhaustive chip level verification plan from the specs Bachelors / Masters in Electrical / Electronics Engineering Preferred Skills/ Experience 5+ years of relevant experience Good in verification approach, flow, concepts and excellent debugging skills Exposure to any other HVLs (System Verilog, VerilogAMS) as a developer / user. Experience in metric based Verification closure using Code and Functional coverage Expertise in automation using Python / Perl / Tcl / shell scripting

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER The Role The focus of this role is to own group specific flow deployment for IP subsystems and SOC. This involves ownership of collaboration with CAD team as well as PD implementation team for synthesis, LEC, CLP, STA and PNR. Key Responsibilities Responsible for physical implementation flow deployment for synthesis, LEC, CLP, STA and PNR Collaborate with central CAD team, DFX, EDA vendors and Design teams to achieve best PPA. Complete quality and bug free flow delivery for 2nm to 7nm. Debug and resolve technical issues in tools as well as flows Preferred Experience Experienced in CAD based physical implementation work flows for synthesis, LEC, CLP, STA and PNR Good to have experience in automation using perl, tcl and python. Good communication skill for collaboration Understand RTL and DFT basics Academic Credentials Bachelors with 5 years of experience or Masters degree with 3 years of experience in Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER The Role The focus of this role is to own group specific flow deployment for IP subsystems and SOC. This involves ownership of collaboration with CAD team as well as PD implementation team for synthesis, LEC, CLP, STA and PNR. Key Responsibilities Responsible for physical implementation flow deployment for synthesis, LEC, CLP, STA and PNR Collaborate with central CAD team, DFX, EDA vendors and Design teams to achieve best PPA. Complete quality and bug free flow delivery for 2nm to 7nm. Debug and resolve technical issues in tools as well as flows Preferred Experience Experienced in CAD based physical implementation work flows for synthesis, LEC, CLP, STA and PNR Good to have experience in automation using perl, tcl and python. Good communication skill for collaboration Understand RTL and DFT basics Academic Credentials Bachelors with 5 years of experience or Masters degree with 3 years of experience in Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.