1074 Dft Jobs - Page 3

Apply to this job We are looking for a highly skilled and experienced DFT Engineer to become part of our team. Our DFT Engineers will build efficient System on Chip (SoC) and IP for data center applications. This role offers the opportunity to work with industry-standard Siemens/Synopsys DFT EDA tools and IEEE standards (1149, 1500, 1687) while contributing to cutting-edge technology. This role includes developing and applying DFT strategies for complex mixed-signal integrated circuits (ICs), ensuring fault coverage and testability. ASIC Implementation, DFT Engineer Responsibilities Develop and implement DFT strategies for mixed-signal ICs, considering factors such as fault coverage, test time, and in-system test Ensure compliance with IEEE standards (1149, 1687) for DFT methodologies and test patterns Conduct fault simulation and coverage analysis to assess the effectiveness of DFT strategies and identify areas for improvement Generate high-quality test patterns using automated test pattern generation (ATPG) tools Verify the correctness of DFT implementation through simulation and hardware testing Collaborate with design/implementation teams to ensure that DFT requirements are met throughout the process Minimum Qualifications Bachelors degree in Electrical Engineering or Computer Engineering 6+ years of experience in DFT for mixed-signal ICs Understanding of DFT concepts, including scan insertion, BIST, and boundary scan In-depth knowledge of DFT EDA tools (Siemens/Synopsys) Familiarity with IEEE standards 1149, 1500, and 1687 Experience with fault simulation and coverage analysis tools Problem-solving and analytical skills Strong communication skills Experience of consistently working under your own initiative, seeking feedback and input where appropriate Proficiently use Siemens/Synopsys EDA tools for DFT-related tasks, including MBIST, scan insertion, and test pattern generation Preferred Qualifications Masters degree in Electrical Engineering or Computer Engineering 10+ years of experience in DFT strategies implementation and development for mixed signal ICs Experience with mixed-signal DFT methodologies Knowledge of scripting languages (e.g., Perl, Python) for automation Experience with hardware testing and debugging About Meta . Equal Employment Opportunity . Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Basic qualifications: Strong academic and technical background in electrical engineering. A Bachelor s degree in EE / Computer is required, and a Master s degree is preferred. 7 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Required experience : Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less. Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level. Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of System Verilog/Verilog. Experience with DFT tools and techniques. Experience in working with IP vendors for both RTL and hard-mac blocks. Good scripting skills in python or Perl Preferred : Good knowledge of design for test (DFT), stuck-at and transition scan test insertion. Familiarity with DFT test coverage and debug. Familiarity with ECO methodologies and tools. Your base salary will be determined based on your experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Demonstrates ability to do PCB Layout designs of Multilayer boards up to 16 layers for Digital, Analog, PS and RF. Demonstrates proficiency on Mentor Graphics ECAD tools like Dxd , Expedition and Valor. Knowledge of PCB Layout design concepts for High speed, PS and RF layouts. Basic concepts of SI, PI and EMC Concepts to design robust layouts is expected. Knowledge about IPC-2221, IPC-610 standards and Class -C Drawing standards. Experience in writing Perl, VB/Python Scripting for Mentor tools is added advantage. Demonstrates basic knowledge of DFx ( fabrication , assembly and DFT) for PCB and PCBA. In Addition: Must be a Team player. Demonstrates proficiency in oral, written communications. Problem solving, innovation/creativity by proposing alternate solutions are expected. Qualification: B. E/B. TECH Electronics/Electrical Experience : 3 to 7 Years Demonstrates ability to do PCB Layout designs of Multilayer boards up to 16 layers for Digital, Analog, PS and RF. Demonstrates proficiency on Mentor Graphics ECAD tools like Dxd , Expedition and Valor. Knowledge of PCB Layout design concepts for High speed, PS and RF layouts. Basic concepts of SI, PI and EMC Concepts to design robust layouts is expected. Knowledge about IPC-2221, IPC-610 standards and Class -C Drawing standards. Experience in writing Perl, VB/Python Scripting for Mentor tools is added advantage. Demonstrates basic knowledge of DFx ( fabrication , assembly and DFT) for PCB and PCBA. In Addition: Must be a Team player. Demonstrates proficiency in oral, written communications. Problem solving, innovation/creativity by proposing alternate solutions are expected. Qualification: B. E/B. TECH Electronics/Electrical Experience : 3 to 7 Years

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can address, and that matter to the world. This is our life s work, to amplify human creativity and intelligence. As an engineer of our Software Quality Assurance (QA) team, you will orchestrate the process of Software Quality for our CAD tools and flows. We develop and support flows for all of NVIDIAs semiconductor products. In addition, the CAD group also develops in-house tools in the area of Design for Test (DFT) using C++, Python, and TCL. You will work on infrastructure and software used to test our complex semiconductor devices. Below are some of the CAD teams activities. We are a diverse team, looking for someone who is not afraid of a challenge. If this is you, come join us today. What you will be doing: Providing hardware, software, and lab support for testing and validation processes. Architecting highly automated and customizable Software Quality processes for design flows using software engineering with modular design and object-oriented techniques. Crafting feature test plans, identifying, and writing test cases based on user requirements, and providing automation of testing. Maintaining regression testing frameworks and developing test reporting mechanisms Performing code reviews, static analysis, and dynamic testing. Continuously delivering high-quality, bug-free Software Applications. Working closely with our diverse team members on flows to provide DFT and methodologies for industry-leading chip designs. Supporting the development of tools using C++/Python/TCL. Working cross-functionally with DFT Methodology, Implementation, and design teams with important DFT tools support. What we need to see: A BS or MS in Electrical Engineering, Computer Science, or Computer Engineering with at least 4+ years of relevant work experience in Software QA role. Knowledge of different software testing techniques, code reviews, code coverage, unit and flow testing, use case testing, random, white, and black box testing. Experience with test management tools such as TestRail or Zephyr. Familiarity with CI/CD tools like Jenkins and GitLab. Strong GenAI, LLM, AI Code Generation skills desirable. Good software design, algorithms, programming and scripting skills in Python, Tcl, or C++ desired. Experience with defect tracking tools such as JIRA. Experience in providing lab software and hardware Ways to stand out from the crowd: Knowledge or experience with DFT is a plus. Knowledge of BDD processes is desirable. Verilog and ASIC design principles, including knowledge of logic cells is a plus. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If youre creative and autonomous, we want to hear from you! #LI-Hybrid

We are seeking a highly experienced Senior Physical Design Engineer with 8+ years of experience in block-level and full-chip physical implementation. The candidate should be proficient in physical design flows and methodologies for advanced technology nodes. Key Responsibilities: Drive physical implementation from RTL to GDSII (floorplanning, placement, CTS, routing) Perform timing analysis, congestion analysis, and physical verification (DRC/LVS) Optimize for performance, power, and area (PPA) Collaborate closely with RTL, STA, DFT, and package teams Own signoff checks (IR drop, EM, Antenna, Crosstalk, etc.) Support tape-out and silicon validation activities Requirements: 8+ years of experience in physical design implementation and signoff Strong hands-on experience with tools like ICC2, Innovus, Primetime, RedHawk, Calibre Solid understanding of timing closure, IR/EM analysis, and power optimization Experience with advanced nodes (7nm, 5nm, etc.) is a plus Good scripting skills (TCL, Perl, Python) for automation Strong communication and teamwork skills

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. . Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design,

Key Responsibilities: Interpret schematics, layouts, BOMs, and datasheets to understand components, their packaging, and PCB requirements. Create and maintain schematic symbols and footprints per: o ANSI Y32.2 / IEEE 315 (US schematic symbols) o IEC 60617 (European standards) o IPC-7351 (land pattern and footprint creation) Design high-quality multi-layer PCBs using Cadence Allegro, Altium Designer, PADS supporting: o Auto-routing o Team collaboration o High-speed/serial signal handling Optimize designs for DFM, DFT, DFA, with emphasis on cost, reliability, and layer reduction. Perform stack-up selection, impedance control, and use constraint managers effectively. Apply EMI/EMC-compliant layout practices and design techniques. Collaborate with mechanical and hardware teams on thermal, mechanical, and signal considerations. Understand PCB materials, fabrication processes, soldering standards, and assembly techniques. Generate fabrication outputs including Gerbers, ODB++, drill files, BOMs, Pick & Place, and mechanical drawings. Conduct thorough reviews for design quality, manufacturability, and compliance to standards. - Required Skills B.Tech in electronics engineering with 5+ years of hands-on PCB layout experience including symbol/footprint creation. Strong understanding of DFM/DFT/DFA, PCB stack-up, HDI, back drilling, and high-volume production optimization. Proficiency with EDA tools: Cadence Allegro, Altium Designer, PADS. Knowledge in EMI/EMC standards and design practices. Familiar with different component manufacturers, packages, specifications, and selection criteria. Strong ability to read datasheets, interpret component specs, and assess mounting/thermal requirements. knowledge of IPC standards: IPC-2221, IPC-7351, IPC-610, etc. Familiar with assembly guidelines, soldering standards, PCB materials, and manufacturing processes. Experience working under AS9100 quality standards and procedure

Job description: Job Description Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ͏ Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project ͏ Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc)2. Self-development Skill test for next level clearance on Trend Nxt ͏ ͏ Mandatory Skills: VLSI Design For Testability - DFT . Experience: 1-3 Years . Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Mission principale : Industrialisation des Moyens de Test Mission 1 : Assurer l’industrialisation des nouvelles solutions de test Rédiger les cahiers des charges selon les spécifications awardés (Temps de test, budget, délai de livraison, Capabilité et R&R) Garantir le bon déroulement des différentes phases du projet dans les parties relatives au Test Développer les moyens de test (Hardware et Software) Contribuer dans les échanges techniques avec le client dans les sujets relatifs au test en collaboration avec le chef de projet. Assurer la réception, validation et qualification des moyens de test Elaborer les couvertures de test Mission 2 : Chiffrer les nouvelles solutions de test Faire l’analyse DFT et assurer une bonne testabilité du produit en collaboration avec l’équipe projet et le client Participer aux choix techniques pour les nouvelles stratégies de test Chiffrer les moyens de test et les potentielles évolutions. Mission 3 : Assurer une productivité et efficience en continu des moyens de test Proposer et concrétiser en continu des pistes d’optimisation des solutions de test Optimiser les temps de test. Améliorer en continu la couverture et la fiabilité des testeurs. Assurer une veille technologique par rapport aux stratégies et moyens de test et de contrôle automatisés. Mission 4 : Assurer un entretien optimal et une efficience de fonctionnement des moyens de test sous sa responsabilité Supporter et former les techniciens Support Test Garantir le fonctionnement des moyens de test selon les spécifications définies depuis le lancement du projet Participer à la validation des interventions préventives sur les moyens de test Participer à la maintenance corrective des testeurs Niveau et spécialité requis : Ingénieur en électronique, électromécanique, mécatronique ou informatique industrielle Expérience professionnelle: 5 ans dans un milieu industriel dans le domaine du test des cartes électroniques.

Expertise / Skills: Footprint creation Layout, high-speed layout,multi-layer board design Orcad (must) Allegro (must) Job Description: Guide and provide technical support to juniors for Project development. Experience in High-speed design and Analog design routing. Experience with PCB Layout design up to 4 layers is preferred. Conduct hardware design in DFM, DFA, and DFT format Should be open to working in a challenging environment with minimal supervision Design and Develop Multilayer PCB Basic knowledge of IPC Standards PCB Design as per the EMI / EMC standards Strong Skills for Library development, footprint creation, and Layout in software like Orcad (must), Altium, Allegro (must), Eagle, Mentor Graphics, etc Demonstrate robust design principles in the execution Continuously upgrade skills and knowledge of self Signal Integrity and Power Integrity. Knowledge of protocols including RS232, RS485, SPI, USB, CAN, ZigBee, Experience in Power supply- SMPS design, DC/DC converter, LDOs

Role: PCB Design & Development: Design and develop RF/Microwave and mixed-signal PCBs for high-frequency applications, including phased arrays and wireless communication systems. Implement repeated circuit designs to ensure consistency and reliability in large-scale deployments. Tool Utilization & Analysis: Utilize Altium Designer to create schematics, layouts, and manufacturing documentation. Perform signal integrity, power integrity, and electromagnetic compatibility (EMC) analyses to optimize PCB performance. Cross-Functional Collaboration: Collaborate with RF, hardware, and software teams to integrate PCB designs into larger system architectures. Work with vendors and fabrication houses to ensure designs meet DFM (Design for Manufacturability) and DFT (Design for Testability) requirements. Required Qualifications Bachelors degree in Electronics and communication . Strong experience in RF and mixed-signal PCB design, including impedance control and high-frequency layout techniques. Proficiency with Altium Designer (or similar PCB design tools). Knowledge of phased array design, including beamforming and antenna integration. Experience with repeated circuit design methodologies for high-volume production. Understanding of RF circuit design principles (e.g., transmission lines, filters, amplifiers, matching networks). Familiarity with simulation tools for RF and PCB analysis (e.g., HFSS, ADS, CST, or similar). Preferred Qualifications Experience with multi-layer PCB stack-ups and mixed-signal isolation techniques. Knowledge of RF packaging, shielding, and thermal management. Previous experience with antenna design and RF front-end modules. Familiarity with manufacturing and assembly processes for RF PCBs. Core Competencies Effective written and verbal communication skills. Ability to explain complex technical concepts to non-technical stakeholders. Strong teamwork and collaboration skills. Ability to work independently and manage multiple projects simultaneously. Excellent organizational skills, attention to detail, and a systems-thinking approach. Willingness to assist teammates with larger engineering tasks and assume technical responsibility when required. Role & responsibilities Preferred candidate profile

EE Department Ahmedabad, Gujarat, India Full Time No of Position: 1 Experience: 3-6 Years Expertise / Skills Footprint creation Layout, high-speed layout,multi-layer board design Orcad (must) Allegro (must) Job Description Guide and provide technical support to juniors for Project development. Experience in High-speed design and Analog design routing. Experience with PCB Layout design up to 4 layers is preferred. Conduct hardware design in DFM, DFA, and DFT format Should be open to working in a challenging environment with minimal supervision Design and Develop Multilayer PCB Basic knowledge of IPC Standards PCB Design as per the EMI / EMC standards Strong Skills for Library development, footprint creation, and Layout in software like Orcad (must), Altium, Allegro (must), Eagle, Mentor Graphics, etc Demonstrate robust design principles in the execution Continuously upgrade skills and knowledge of self Signal Integrity and Power Integrity. Knowledge of protocols including RS232, RS485, SPI, USB, CAN, ZigBee, Experience in Power supply- SMPS design, DC/DC converter, LDOs Apply Now

Location :- Bangalore Experience :- 12-20 years Required Skills And Experience: This role is for a Principal DFT engineer with 15 years plus experience Technical leadership in DFT and ability to train/work with junior team members Experience with Perl, TCL, and/or python with ability to build and deploy generic DFT flows Proficient in Unix/Linux environments One or more core DFT skills are considered crucial for this position including some of the following Knowledge of at-speed testing, test insertion and test coverage assessment, test pattern development, scan compression, Memory BIST, Logic BIST, JTAG, IJTAG, fault simulation, debug, verification, SSN, designing and conducting experiments/tool evaluations. Experience with Siemens, Cadence and/or Synopsys DFT tools Qualified candidates will have a university degree (or equivalent) in Electronic Engineering, Computer Engineering, or other relevant technical subject area.

Experience: 5 + Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPGgeneration & Simulations along with Pattern Porting/re-targeting and Coverage improvement Experience with Scan, Compression, ATPG and simulations withSynopsys EDAtools. Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Excellent Customer interaction, Communication and Team work skills Skills Required Cadence Tools, Automatic Test Pattern Generation (ATPG), DFT, Memory Built-In Self Test (MBIST),Scan Insertion Location Hyderabad, India Desirable Skills Cadence Tools, Automatic Test Pattern Generation (ATPG), DFT, Memory Built-In Self Test (MBIST),Scan Insertion Designation Associate

Hi All, Greetings from Eximietas...! Position: Senior DFT Engineers/Leads/Architects Location: Visakhapatnam Mode of Work: On-site Exp: 5 to 15 Years We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. Job Overview: Must be able to obtain and maintain a Department of Defense classified clearance Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT) Should possess intimate knowledge of DFT insertion flows Basic scan chain insertion using synthesis or other software tools Experience in compression scan insertion, LBIST and other scan technologies Intimate knowledge of memory build-in self-test (MBIST) Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals Debug and Analysis of failures to improve fault coverage Verification of ATPG testbenches and debugging root cause of simulation mis-compares Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687 Knowledge of timing analysis and equivalency checks would be added bonus Ability to work in collaborative team environment Should be able to finish DFT tasks independently Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers Self-driven and committed individual who can work in a fast-paced project environment This job might be for you if : You enjoy solving problems and love tackling difficult challenges with creative solutions. You persistently seek answers even when they are not readily available. You communicate clearly and write well . You are motivated, driven, and take initiative without waiting to be asked. You take ownership of your work and strive to make a difference. You can impress customers with your enthusiasm and ability to solve their issues. Qualifications: Bachelor’s degree in Computer Science, Electrical/Electronics Engineering , or a related field.

Hello All, Eximietas Design Hiring STA Engineers/Leads Experience: 5+ Years Job Description: Experience in Static Timing Analysis (STA) for ASIC designs. Experience in developing timing constraints. Experience in timing closure and optimization. Proficiency in using scripting languages such as Perl and TCL. Familiarity with EDA tools such as PrimeTime and Design Compiler. Experience in Physical Design and/or DFT is a plus. Bachelor’s or Master’s degree in Electrical/Electronics/Computer Science Engineering or related field. Interested Engineers, please share your updated resume: maruthiprasad.e@eximietas.design

Hi All, Greetings from Eximietas...! Position: Senior DFT Engineers/Leads/Architects Location: Visakhapatnam Mode of Work: On-site Exp: 5 to 15 Years We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. Job Overview: Must be able to obtain and maintain a Department of Defense classified clearance Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT) Should possess intimate knowledge of DFT insertion flows Basic scan chain insertion using synthesis or other software tools Experience in compression scan insertion, LBIST and other scan technologies Intimate knowledge of memory build-in self-test (MBIST) Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals Debug and Analysis of failures to improve fault coverage Verification of ATPG testbenches and debugging root cause of simulation mis-compares Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687 Knowledge of timing analysis and equivalency checks would be added bonus Ability to work in collaborative team environment Should be able to finish DFT tasks independently Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers Self-driven and committed individual who can work in a fast-paced project environment This job might be for you if : You enjoy solving problems and love tackling difficult challenges with creative solutions. You persistently seek answers even when they are not readily available. You communicate clearly and write well . You are motivated, driven, and take initiative without waiting to be asked. You take ownership of your work and strive to make a difference. You can impress customers with your enthusiasm and ability to solve their issues. Qualifications: Bachelor’s degree in Computer Science, Electrical/Electronics Engineering , or a related field.

Hi All, Greetings from Eximietas...! Position: Senior DFT Engineers/Leads/Architects Location: Visakhapatnam Mode of Work: On-site Exp: 5 to 15 Years We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. Job Overview: Must be able to obtain and maintain a Department of Defense classified clearance Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT) Should possess intimate knowledge of DFT insertion flows Basic scan chain insertion using synthesis or other software tools Experience in compression scan insertion, LBIST and other scan technologies Intimate knowledge of memory build-in self-test (MBIST) Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals Debug and Analysis of failures to improve fault coverage Verification of ATPG testbenches and debugging root cause of simulation mis-compares Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687 Knowledge of timing analysis and equivalency checks would be added bonus Ability to work in collaborative team environment Should be able to finish DFT tasks independently Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers Self-driven and committed individual who can work in a fast-paced project environment This job might be for you if : You enjoy solving problems and love tackling difficult challenges with creative solutions. You persistently seek answers even when they are not readily available. You communicate clearly and write well . You are motivated, driven, and take initiative without waiting to be asked. You take ownership of your work and strive to make a difference. You can impress customers with your enthusiasm and ability to solve their issues. Qualifications: Bachelor’s degree in Computer Science, Electrical/Electronics Engineering , or a related field.

THE ROLE: As a member of the G&E SoC DFT Team, the successful candidate will own the DFX timing responsibilities for the next gen of AMD SoCs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: The candidate must have thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. DFX timing constraints development Review timing reports Timing closure for different modes : AC/DC scan capture , scan shift , MBIST Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture DFX timing constraints development Review timing reports Timing closure for different modes : AC/DC scan capture , scan shift , MBIST Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Proficient in logic design using Verilog Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

THE ROLE: Be a member of the team that plays a significant role in ensuring the quality of next generation microprocessors through structured DFT, Automatic Test Pattern Generation (ATPG) and Logic Built-In Self-Test (LBIST) techniques. Key responsibilities: Collaborating with the design teams to ensure DFT design rules and guidelines are met The person should have experience in timing concepts Generating high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test compression techniques Exercising the LBIST circuitry and ensuring that repeatable signatures can be produced Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, improving and maintaining scripts as vital Desired profile - The candidate must have detailed knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Experience with test tools such as FastScan and TestKompress is highly desirable.Scan/ATPG, knowledge of industry standard DFT features, simulation debug, MBIST Academic credentials: MS/M Tech/BE in Computer Engineering/Electronics/Electrical Engineering Demonstrated success in a senior ICteam role with similar skills Location: Hyderabad Telangana

MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs.?As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of DesignforTest methodologies and DFT verificationexperience (eg.IEEE1500, JTAG 1149.x, Scan, memory BISTetc.) Experience with Mentortestkompressand/or SynopsysTetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

THE ROLE: Be a member of the team that plays a significant role in ensuring the quality of next generation microprocessors through structured DFT, Automatic Test Pattern Generation (ATPG) and Logic Built-In Self-Test (LBIST) techniques. Key responsibilities: Collaborating with the design teams to ensure DFT design rules and guidelines are met The person should have experience in timing concepts Generating high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test compression techniques Exercising the LBIST circuitry and ensuring that repeatable signatures can be produced Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, improving and maintaining scripts as vital Desired profile - The candidate must have detailed knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Experience with test tools such as FastScan and TestKompress is highly desirable.Scan/ATPG, knowledge of industry standard DFT features, simulation debug, MBIST Academic credentials: MS/M Tech/BE in Computer Engineering/Electronics/Electrical Engineering Demonstrated success in a senior ICteam role with similar skills Location: Hyderabad Telangana AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

THE ROLE: We are looking for an adaptive, self-motivated design for test verification engineer to join our growing server SOC DFT team. Identified candidate will be responsible for high quality verification of our DFT features for next generation server SOCs. This team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion design for test, and verification. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Create and execute test plans for DFT features for next generation EPYC server SOCs. Carryout verification of DFT features such as JTAG/1500/1687, MBIST, Scan, Fuse, Clocks, Resets, high speed IO testing and much more at SOC level. Will be creating test bench and verification infra using SV or C++. Debug regression test failures and root cause design issues, identify verification gaps and address the same. Debug fails and root cause them to design / verification issues. Planning and projecting timelines for areas owned such as test plan creation, test writing, development of verification components, pattern generation etc. Collaborate with large set of stakeholders such as architects, design engineers, functional verification engineers, post silicon engineers etc. Work on code and functional coverage. Generate patterns for post silicon testing and support ATE bring up. Carryout post silicon debugs and help post silicon team achieve high coverage. Work on emulation platforms to augment verification. PREFERRED EXPERIENCE: Prior experience in verifying DFT features at subsystem / SOC level. Proficient in standard simulation & debug tools?such as VCS, Verdi etc. Experienced with Verilog, C, C++, Linux and Windows environments. Scripting language experience: Perl, Python,Ruby, Makefile, shell preferred. Knowledge in few of the DFT features such as JTAG, Memory BIST, Logic BIST, Scan, ATPG is highly desirable Exposure to post silicon debugs and bring up highly is desired.

KEY RESPONSIBILITIES: ? Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues? Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements ? PREFERRED EXPERIENCE: ? Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools? Proficient in using UVM test benches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++?? Graphics pipeline knowledge Developing UVM based verification frameworks and test benches, processes and flows Automating workflows in a distributedcomputeenvironment.?? Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts andSystem Veriloglanguage Good working knowledge ofSystem Cand TLM with some related experience.?? Scripting language experience: Perl, Ruby,Make file, shell preferred.?? Exposure to leadership or mentorship is an asset Desirableassetswith prior exposure to video codec system or other multimedia solutions.?? ? ACADEMIC CREDENTIALS: ? Bachelors orMastersdegree in computer engineering/Electrical Engineering#LI-NS1

Bengaluru, Karnataka Job ID JR2025464648 Category Engineering - Electronic and Electrical Role Type Onsite Post Date Jul. 24, 2025 Job Description At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us. Overview As a leading global aerospace company, Boeing develops, manufactures, and services commercial airplanes, defense products and space systems for customers in more than 150 countries. As a top U.S. exporter, the company leverages the talents of a global supplier base to advance economic opportunity, sustainability, and community impact. Boeing’s team is committed to innovating for the future, leading with sustainability, and cultivating a culture based on the company’s core values of safety, quality, and integrity. Technology for today and tomorrow The Boeing India Engineering & Technology Center (BIETC) is a 5500+ engineering workforce that contributes to global aerospace growth. Our engineers deliver cutting-edge R&D, innovation, and high-quality engineering work in global markets, and leverage new-age technologies such as AI/ML, IIoT, Cloud, Model-Based Engineering, and Additive Manufacturing, shaping the future of aerospace. People-driven culture At Boeing, we believe creativity and innovation thrives when every employee is trusted, empowered, and has the flexibility to choose, grow, learn, and explore. We offer variable arrangements depending upon business and customer needs, and professional pursuits that offer greater flexibility in the way our people work. We also believe that collaboration, frequent team engagements, and face-to-face meetings bring Inclusive perspectives and thoughts – enabling every voice to be heard and every perspective to be respected. No matter where or how our teammates work, we are committed to positively shaping people’s careers and being thoughtful about employee wellbeing. At Boeing, we are inclusive and transformative. With us, you can create and contribute to what matters most in your career, community, country, and world. Join us in powering the progress of global aerospace. Boeing India Engineering has an immediate opening for an Engineering Manager - Digital Circuitswho will be responsible for development and management of engineers in India to perform engineering work-statements for Boeing product life cycle management. This position will work collaboratively with teams from across the globe in an integrated design environment to help deliver an engineering statement of work. The selected individual will develop and handle Engineers, interact with the program leaders from across the globe, with a vision to grow ownership in execution with their team. This position will be in Bengaluru, India , and will be reporting directly to the Sr. Electronic Manager, India. Primary Responsibilities: Manage employees performing engineering and technical activities in the areas of ASIC/FPGA verification and design. Develops and executes integrated departmental plans, policies and procedures and provides input on departmental business and technical strategies, goals, objectives. Acquires resources for department activities, provides technical management of suppliers and leads process improvements. Develops and maintains relationships and partnerships with customers, stakeholders, peers, partners and direct reports. Provides oversight and approval of technical approaches, products and processes. Provides project/Activity planning, and key milestone tracking. Manages post silicon debug support activities for validation, SW development and Test Team. Manages directly (including people reporting) the RTL, DV and DFT primarily. Integrated PD and Emulation activities Understand complex protocols and create implementable objectives for team, Protocols would include PCIe, ARINC, MIL 1553, USB, I2C and other proprietary protocols related to space and flight systems Manages, develops and motivates employees along with functional capability planning. Build capability and capacity upon SV & UVM. Nurture directed test case scenarios using VHDL and similar platforms. Should have strong verbal and written communication skills. Basic Qualifications (Required skills/experience): Bachelor’s degree or higher is required At least 12 years of experience in Digital IC design and verification, involved in at least 3 Chip Tape outs or equivalents. Proficient in tools such as Vmanager and similar tools with other EDA vendors to track and maintain verification workflow metrics for the team. Proficient in concepts such as cross domain clock sync, polymorphism. Proficient in validating the verification workflow with available limitations on tools and resources to provide maximum functional coverage on priority. Demonstrated success leading development efforts, including project management and earned value tracking. Preferred Qualifications (Desired skills/experience): Experience leading or managing in an engineering organization. Familiarity with FAA DO-254 certification. Familiar with Emulation and Safety Flow Analysis Familiar in Formal Verification techniques Familiar in Design Concepts US Person as defined by 22 C.F.R § 120.15 is advantageous. Familiar with LOR verification based VCRM structure Typical Education & Experience: Education/experience typically acquired through advanced education (e.g. Bachelor) and typically 13 to 16 years' related work experience or an equivalent combination of education and experience (e.g. Master+12 years of related work experience etc.) Applications for this position will be accepted until Aug. 02, 2025 Export Control Requirements: This is not an Export Control position. Education Bachelor's Degree or Equivalent Required Relocation This position offers relocation based on candidate eligibility. Visa Sponsorship Employer will not sponsor applicants for employment visa status. Shift Not a Shift Worker (India) Equal Opportunity Employer: We are an equal opportunity employer. We do not accept unlawful discrimination in our recruitment or employment practices on any grounds including but not limited to; race, color, ethnicity, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military and veteran status, or other characteristics covered by applicable law. We have teams in more than 65 countries, and each person plays a role in helping us become one of the world’s most innovative, diverse and inclusive companies. We are proud members of the Valuable 500 and welcome applications from candidates with disabilities. Applicants are encouraged to share with our recruitment team any accommodations required during the recruitment process. Accommodations may include but are not limited to: conducting interviews in accessible locations that accommodate mobility needs, encouraging candidates to bring and use any existing assistive technology such as screen readers and offering flexible interview formats such as virtual or phone interviews. Your Benefits No matter where you are in life, our benefits help prepare you for the present and the future. Competitive base pay and incentive programs. Industry-leading tuition assistance program pays your institution directly. Resources and opportunities to grow your career. Up to $10,000 match when you support your favorite nonprofit organizations.