1672 Dft Jobs - Page 6

Job Description We are seeking a highly skilled and experienced DFT Engineer to join our dynamic team of engineers to develop the next-generation Flash Controllers. As an SoC DFT Engineer, you will be responsible for defining and implementing industry leading DFT solutions, with emphasis on SCAN, MBIST, BSDL etc. The ideal candidate will have a deep understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG & Simulation expertise. ESSENTIAL DUTIES AND RESPONSIBILITIES: DFT Architecture definitions for SoC development Leading complex activities and providing solutions for complex DFT problems. Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs. Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies. Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs. Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology. Qualifications B.Tech / M,Tech / Phd in Electronics, Computer science or Electrical Engineering Minimum 15+ years of experience in DFT Strong understanding of DFT Architecture SKILLS

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description You will be working with our DFT team in Hyderabad to develop DFT tests. These tests are intended to catch manufacturing defects in targeted IPs inside FPGA/SoC. In this role you will have an opportunity to understand in depth FPGA/SoC silicon architectures, ATPG, MBIST Verification at full chip level, DFT/Testability hooks in Silicon, methods and principles to develop ATPG/Functional test vectors, simulate, debug and generate patterns for production tests. You will work closely with Architects, Design engineers, Verification engineers and Software engineers across the globe to ensure FPGA division deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills are required. Requirements/Qualifications Required Skills and Experience Understanding basics of DFT structures (OCC, SSN, SIB, WBRs, compression engine), ATPG(Intest/Extest) , MBIST, Boundary Scan (IEEE 1149.1) Tap Controller, Generating, verifying and debugging test patterns at block and chip-level retargeting to test the designs and firmware for new FPGA families. Improving, extending and porting existing manufacturing test designs to all FPGA family members. Test specification, plan, and documentation BS or MS in EE with 5 to 6 years of experience of working in DFT Hands on experience with industry standard ATPG tools, MBIST, pattern simulation and debugging skills at block and chip-level. Hands-on experience with Verilog behavioral RTL and Gate level netlist. Comfortable with Unix, Perl and/or Shell scripting and familiar with Revision Control (CVS, SVN, …) Strong analytical and problem-solving skills Excellent communication, documentation and presentation skills. Must have strong self-learning ability and enjoy working in teams spread across globe. Good programming skill/Firmware development skills with C, C++/assembly will be a big plus. Exposure to ASIC/FPGA design flow and methodology is a plus (HDL, synthesis, static timing analysis, constraining, Place & Route) Education And Qualifications 7-8 years of professional experience in digital design and DFT Bachelor of Engineering with Diploma in VLSI /Master of Science / Engineering Degree. Travel Time 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

We aspire to be world-leader in innovative telecom and security solutions by offering cutting-edge, high-performance telecom and security solutions to business customers. Our Mission is simple. To prove that Indian engineers can design, develop, and manufacture world-class technology products for customers across the world, right from India. Join our team of like-minded engineers, applied researchers, and technocrats with the will, courage, and madness to achieve this mission! Why work at Matrix Matrix fully integrates software and hardware across its products. Engineers here collaborate more effectively to create solutions that solve real problems and make an impact. We are responsible for every nut, bolt, and line of code in our products! As an engineer, your involvement will be critical in the entire lifecycle of a product - right from ideation-development-production-deployment. Get to feel the sense of accomplishment that comes with creating something that solves a real and pressing problem and is used by scores of customers. Job Description Role : Hardware Design Engineer/ Sr. Engineer - (PCB/ CAD) Function : Hardware Design - (PCB/ CAD) Work Location : Vadodara, Gujarat Who are you You are an energetic and passionate PCB/CAD Design Engineer with a strong background in PCB layout design. You have experience working on high-speed and complex boards, and you excel at using CAD tools to create precise and efficient designs. Your expertise and enthusiasm drive you to tackle challenging projects and deliver high-quality results. Experience : 2+ Years Qualification : B.E/ B.tech/ M.E/ M.tech (EC, Electronics & Communication) OR MSc (EC/Electronics) Technical Skills Required : Good understanding of Datasheets, Library creation for Complex Logical and Footprints. IPC Standards for Footprint Creation and Layout process Exposure to all relevant IPC standards & MIL Standard design practices PCB Designing flow from Library creation to Gerber release to FAB. High speed Constraints setting and routing. Should have worked on High Speed signal routing . Hands-on experience in Designing High-speed, Multilayer PCB designs DFM checks, DFx (DFA, DFM & DFT) checks Should have hands-on expertise on standard High Speed Digital, Analog & Mixed signal Design ,I2C,SPI, USB2.0/3.0, Ethernet, PoE, BLE, Wi-fi, GSM, TFT LCD, DDR2/DDR3/DDR4, SD Card, NAND, MIPI , Optical interface etc. DRC and Post-processing (Gerber Settings, FAB & Assembly files generation) Quality checks for Footprints, PCB Layout file, FAB & Assembly files Interaction with Design, Mechanical, SI, PI, Thermal, FAB, Assembly house for Clarification and Reviews Good communication skills and should be able to handle projects independently EDA Tools: Mentor Expedition. Valor Gerber tools for reviews How Your Day Might Look Like Check datasheets to update and create accurate PCB component libraries. Design and adjust PCB layouts following industry standards. Handle the entire PCB design process, from creating libraries to preparing files for manufacturing. Set up and test high-speed signals to ensure everything works properly. Work on complex, multilayer PCB designs, focusing on signal integrity and layout. Perform Design for Manufacturing (DFM) checks to make sure designs are ready for production. Check design rules and finalize files for fabrication and assembly. Review and verify designs with design, mechanical, signal integrity, power integrity, thermal, and assembly teams. Manage your projects, making sure everything stays on track from start to finish. What we offer Opportunity to work for an Indian Tech Company creating incredible products for the world, right from India Be part of a challenging, encouraging, and rewarding environment to do the best work of your life Competitive salary and other benefits Generous leave schedule of 21 days in addition to 9 public holidays, including holiday adjustments to convert weekends into long weekends 5-day workweek with 8 flexi-days months, allowing you to take care of responsibilities at home and work Company-paid Medical Insurance for the whole family (Employee+Spouse+Kids+Parents). Company paid Accident Insurance for the Employee On-premise meals, subsidized by the company If you are an Innovative Tech-savvy individual, Look no further. Click on Apply and we will reach out to you soon!

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT . Experience: 3-5 Years .

We aspire to be world-leader in innovative telecom and security solutions by offering cutting-edge, high-performance telecom and security solutions to business customers. Our Mission is simple. To prove that Indian engineers can design, develop, and manufacture world-class technology products for customers across the world, right from India. Join our team of like-minded engineers, applied researchers, and technocrats with the will, courage, and madness to achieve this mission! Why work at Matrix Matrix fully integrates software and hardware across its products. Engineers here collaborate more effectively to create solutions that solve real problems and make an impact. We are responsible for every nut, bolt, and line of code in our products! As an engineer, your involvement will be critical in the entire lifecycle of a product - right from ideation-development-production-deployment. Get to feel the sense of accomplishment that comes with creating something that solves a real and pressing problem and is used by scores of customers. Job Description Role : Hardware Design Engineer/ Sr. Engineer - (PCB/ CAD) Function : Hardware Design - (PCB/ CAD) Work Location : Vadodara, Gujarat Who are you You are an energetic and passionate PCB/CAD Design Engineer with a strong background in PCB layout design. You have experience working on high-speed and complex boards, and you excel at using CAD tools to create precise and efficient designs. Your expertise and enthusiasm drive you to tackle challenging projects and deliver high-quality results. Experience : 2+ Years Qualification : B.E/ B.tech/ M.E/ M.tech (EC, Electronics & Communication) OR MSc (EC/Electronics) Technical Skills Required : Good understanding of Datasheets, Library creation for Complex Logical and Footprints. IPC Standards for Footprint Creation and Layout process Exposure to all relevant IPC standards & MIL Standard design practices PCB Designing flow from Library creation to Gerber release to FAB. High speed Constraints setting and routing. Should have worked on High Speed signal routing . Hands-on experience in Designing High-speed, Multilayer PCB designs DFM checks, DFx (DFA, DFM & DFT) checks Should have hands-on expertise on standard High Speed Digital, Analog & Mixed signal Design ,I2C,SPI, USB2.0/3.0, Ethernet, PoE, BLE, Wi-fi, GSM, TFT LCD, DDR2/DDR3/DDR4, SD Card, NAND, MIPI , Optical interface etc. DRC and Post-processing (Gerber Settings, FAB & Assembly files generation) Quality checks for Footprints, PCB Layout file, FAB & Assembly files Interaction with Design, Mechanical, SI, PI, Thermal, FAB, Assembly house for Clarification and Reviews Good communication skills and should be able to handle projects independently EDA Tools: Mentor Expedition. Valor Gerber tools for reviews How Your Day Might Look Like Check datasheets to update and create accurate PCB component libraries. Design and adjust PCB layouts following industry standards. Handle the entire PCB design process, from creating libraries to preparing files for manufacturing. Set up and test high-speed signals to ensure everything works properly. Work on complex, multilayer PCB designs, focusing on signal integrity and layout. Perform Design for Manufacturing (DFM) checks to make sure designs are ready for production. Check design rules and finalize files for fabrication and assembly. Review and verify designs with design, mechanical, signal integrity, power integrity, thermal, and assembly teams. Manage your projects, making sure everything stays on track from start to finish. What we offer Opportunity to work for an Indian Tech Company creating incredible products for the world, right from India Be part of a challenging, encouraging, and rewarding environment to do the best work of your life Competitive salary and other benefits Generous leave schedule of 21 days in addition to 9 public holidays, including holiday adjustments to convert weekends into long weekends 5-day workweek with 8 flexi-days months, allowing you to take care of responsibilities at home and work Company-paid Medical Insurance for the whole family (Employee+Spouse+Kids+Parents). Company paid Accident Insurance for the Employee On-premise meals, subsidized by the company If you are an Innovative Tech-savvy individual, Look no further. Click on Apply and we will reach out to you soon!

As a Financial Analyst in our Financial Planning & Analysis (FP&A) team based in Pune, you will play a crucial role in supporting the team's efforts in Financial Planning, Reporting, and Analysis. This position is ideal for someone at the early stages of their finance career who is eager to gain practical experience while working alongside senior team members. Your responsibilities will include assisting in the preparation of routine financial reports and dashboards by collecting and consolidating data from various sources such as Finance, Accounting, and Business Ops. You will also be involved in supporting the monthly, quarterly, and annual planning processes by updating templates, monitoring submissions, and ensuring data accuracy. Additionally, you will help in creating senior management presentations under the guidance of senior analysts, ensuring timely delivery of accurate data and visuals. You will be expected to conduct thorough variance analysis to identify trends or anomalies in financial performance. Furthermore, you will provide assistance in plant and division-level financial reporting activities, as well as tracking KPIs and financial metrics. As part of your role, you will also engage in ad-hoc analyses and project support as assigned by senior analysts or the FP&A lead. To qualify for this position, you should possess a Bachelor's degree in Business Administration with a focus on Finance, Mathematics, Statistics, Economics, or have relevant experience in core finance. Candidates with an Accounting major (B.Com) and certifications such as CA, ICWA, or CFA are highly encouraged to apply. The ideal candidate will have 1-3 years of experience, preferably in the manufacturing industry. Proficiency in tools like OBIEE, SAP, PowerBI Development, SQL, and working knowledge of Business Intelligence Tools such as SAP, Oracle, ENCORE, RADAR, and DFT will be advantageous. Strong analytical skills are essential for interpreting financial data effectively. You should also possess excellent organizational and time management skills, along with the ability to interact with stakeholders at all levels of the organization. Demonstrated expertise in implementing Process Improvement tools and methodologies across businesses is a plus. As a highly motivated individual, you are expected to have exceptional oral and written communication skills. Building and maintaining productive relationships with key internal clients, including business units, operations, and colleagues, will be a critical aspect of this role. If you are looking to grow your career in finance and have the required qualifications, we encourage you to apply for this exciting opportunity.,

TechShlok is expanding its design team and looking to add a PCB Design Engineer to the R&D unit to accelerate the development across multiple projects. As a PCB Design Engineer at TechShlok, your main responsibility will be to perform end-to-end PCB layout, including component placement, routing, and generating manufacturing files. You will design multi-layer boards (4 layers and above) with adherence to industry standards, signal integrity, and EMI/EMC best practices. It is essential to ensure optimal routing of high-speed signals (e.g., DDR, PCIe, USB, high-speed LVDS) and differential pairs. You will also be responsible for generating comprehensive documentation, including Gerber files, assembly drawings, and BOMs. Collaboration with cross-functional teams (electrical, mechanical, and test engineers) is crucial to align design requirements and constraints. Effective communication with fabrication and assembly vendors to address DFM (Design for Manufacturability) and DFT (Design for Test) issues is required. During your first 30 days at TechShlok, you will complete onboarding, learn team workflows, and familiarize yourself with PCB design tools, libraries, and version control. You will review existing designs, standards, and DFM/DFT guidelines, and assist in simple board modifications under senior guidance. In the next 30 days (Day 31-60), you will take on a small-to-medium complexity PCB design project, participate in design reviews, refine routing and stack-up skills, and engage with manufacturing partners for DFM insights. You will also focus on enhancing workflow efficiency and documentation methods. During the final 30 days (Day 61-90), you will independently handle a complex 4-layer board design project, collaborate with QA/testing to ensure reliability and testability, recommend improvements in processes and design tools, and contribute to the technical strategy while mentoring junior team members. The ideal candidate for this role should have a Bachelor's degree in Electronics Engineering or a related field, 3 to 5 years of experience in PCB designing, proficiency in tools like Kicad, Eagle, or Altium, and a strong understanding of PCB stack-up design, impedance control, and high-speed routing constraints. Familiarity with IPC standards and best practices for PCB fabrication and assembly, excellent written and verbal communication skills, and the ability to collaborate effectively in a cross-functional team setting are essential. Experience working with various PCB materials and advanced technologies, familiarity with power distribution network analysis and thermal management techniques, and exposure to simulation tools for signal integrity and EMI/EMC considerations are considered good-to-have skills.,

Role & responsibilities Description: Performs semiconductor design engineering assignments including engineering and designing chip layout circuits, circuit checking, documenting specifications, modifying and evaluating semiconductor devices and components. Reviews product requirements and logic diagrams for device definition. Typically responsible for projects, or portions of projects, to design, fabricate, modify, and evaluate semiconductor devices and components. 3-5 years of experience Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Experience with Gate Level Simulations and timing debugs. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Additional Details TSMC Certification:- Added Advantage

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

Job Summary Design and Development using Java. Micro services design and development. Explore building wrapper APIs and to expose them into API Gateway / KONG – this requires a fair amount of knowledge on RESTful services. Understand user requirements in detail and break it into high level & low-level design Document the requirement by writing the technical specification document Strong stakeholder management skills – both technical and business users Review code and be part of SIT and UAT Conduct the UT for all the codes developed Conduct the System & Integration Testing of application Participate and coordinate among stakeholders in SIT/UAT and work along with the teams in articulating the requirements Preparing Test Strategy and Test Scenarios to ensure the Test Environment standards are followed by the team. Responsible for production rollouts and change implementations followed by successful UVT Post implementation warranty support and communication to stakeholders on the implementation Coordinate for the production / UAT / SIT deployment Conduct peer-review on the co-developer's deliverables Follow Agile concepts / processes and JIRA workflows firmly Responsibilities Strategy Hands-on experience Strong in developing using Java, J2EE Strong technical skills in the areas of core Java, JSP/Servlet, J2EE design patterns, REST Services (using Spring, Spring Boot) Hands on experience in Micro Services design & containerization technologies Hands on in any of the Java Scripting frameworks – ReactJS, AngularJS, Dojo Hands on in Database – DB Design, SQL, Stored Procedures writing etc. Strong in DevOps tools (Git, BitBucket, Artifactory, Ansible, Maven, Jenkins, Rundeck) Deployment skills in any application servers (WAS, Jboss, Tomcat) Strong DevOps experience Business Awareness and understanding of the Content Management platform. Processes Responsible to manage the Filenet platform People & Talent Strong knowledge communication (written and verbal) skills Should have worked in Agile environment Should possess strong collaborative skills Should be proactive and have leadership skills Governance Thorough knowledge to be gained on Bank’s governance model and process and update time to time to get implemented within team Regulatory & Business Conduct Display exemplary conduct and live by the Group’s Values and Code of Conduct. Take personal responsibility for embedding the highest standards of ethics, including regulatory and business conduct, across Standard Chartered Bank. This includes understanding and ensuring compliance with, in letter and spirit, all applicable laws, regulations, guidelines and the Group Code of Conduct. Lead the [country / business unit / function/XXX [team] to achieve the outcomes set out in the Bank’s Conduct Principles: [Fair Outcomes for Clients; Effective Financial Markets; Financial Crime Compliance; The Right Environment.] * Effectively and collaboratively identify, escalate, mitigate and resolve risk, conduct and compliance matters. [Insert local regulator e.g. PRA/FCA prescribed responsibilities and Rationale for allocation]. [Where relevant - Additionally, for subsidiaries or relevant non -subsidiaries] Serve as a Director of the Board of [insert name of entities] Exercise authorities delegated by the Board of Directors and act in accordance with Articles of Association (or equivalent) Other Responsibilities Embed Here for good and Group’s brand and values in XXXX [country / business unit / team]; Perform other responsibilities assigned under Group, Country, Business or Functional policies and procedures; Multiple functions (double hats); [List all responsibilities associated with the role] Skills And Experience FileNet ,Datacap Java,SQL Production Support About Standard Chartered We're an international bank, nimble enough to act, big enough for impact. For more than 170 years, we've worked to make a positive difference for our clients, communities, and each other. We question the status quo, love a challenge and enjoy finding new opportunities to grow and do better than before. If you're looking for a career with purpose and you want to work for a bank making a difference, we want to hear from you. You can count on us to celebrate your unique talents and we can't wait to see the talents you can bring us. Our purpose, to drive commerce and prosperity through our unique diversity, together with our brand promise, to be here for good are achieved by how we each live our valued behaviours. When you work with us, you'll see how we value difference and advocate inclusion. Together We Do the right thing and are assertive, challenge one another, and live with integrity, while putting the client at the heart of what we do Never settle, continuously striving to improve and innovate, keeping things simple and learning from doing well, and not so well Are better together, we can be ourselves, be inclusive, see more good in others, and work collectively to build for the long term What We Offer In line with our Fair Pay Charter, we offer a competitive salary and benefits to support your mental, physical, financial and social wellbeing. Core bank funding for retirement savings, medical and life insurance, with flexible and voluntary benefits available in some locations. Time-off including annual leave, parental/maternity (20 weeks), sabbatical (12 months maximum) and volunteering leave (3 days), along with minimum global standards for annual and public holiday, which is combined to 30 days minimum. Flexible working options based around home and office locations, with flexible working patterns. Proactive wellbeing support through Unmind, a market-leading digital wellbeing platform, development courses for resilience and other human skills, global Employee Assistance Programme, sick leave, mental health first-aiders and all sorts of self-help toolkits A continuous learning culture to support your growth, with opportunities to reskill and upskill and access to physical, virtual and digital learning. Being part of an inclusive and values driven organisation, one that embraces and celebrates our unique diversity, across our teams, business functions and geographies - everyone feels respected and can realise their full potential.

Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI , and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 . Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation , working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role in the AECG ASIC organization is to provide hands-on technical leadership in developing microarchitecture, implementing the design in RTL, RTL Integration etc. ensuring quality (design checks and verification reviews) and PD support for next generation ASICs THE PERSON: You have a passion for modern, complex SoC architecture with various IO peripherals and heterogeneous processor systems and digital design & verification in general. You are a team player who has excellent communication skills and experience collaborating in a corporate environment with other architects & engineers located in different sites/time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Define and specify micro-architecture of ASIC building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements RTL design and debug of complex blocks in Verilog / System Verilog Analyze design metrics and make implementation choices to optimize PPA RTL Integration Work with implementation, verification and physical design teams to achieve high quality design and successful tape out Address customer problems through innovative enhancements to product architecture/ micro-architecture Collaborate with cross-functional teams to solve novel problems across multiple functional areas in development of clocking features and/or algorithms Lead internal and external teams for RTL design PREFERRED EXPERIENCE: 8+years of experience in an ASIC RTL Design execution role leading to an understanding of end-end development. Strong foundation in SoC architecture and processor systems with proven years of experience Good analytical problem solving, and attention to details Excellent written and verbal communication skills Knowledge of CPU, AXI Interconnect, and I/O peripherals Knowledge of SOC development flow and accelerator IP ASIC design flow and direct experience with ASIC RTL design and Integration. Digital design and experience with RTL design in Verilog/System Verilog Circuit timing/STA, and practical experience with Prime Time or equivalent tools Low power digital design and analysis Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation TCL, Perl, Python scripting Version control systems such as Perforce, ICManage or Git Strong verbal and written communication skills Ability to organize and present complex technical information Fluent in working with Linux environment ACADEMIC CREDENTIALS: BE, B.Tech, BS, ME, MTech, or MS degree in in Electronics, Electrical or Computer Engineering. Hands-on Experience in design and integration of complex subsystems or SOC level integration, quality cleanup and delivery to DV, physical design teams. Strong understanding of SOC globals like clocking, reset, boot and power management flows, low power design techniques, security Strong technical leader who communicates well with great collaboration skills Good understanding of other domains like pre-si verification, Synthesis, and physical design #LI-SR4 Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Responsibilities Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 3+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

What youll have 12+ Years of experience in developing and implementing DFT architecture and test strategies for complex ASIC/SoC Designs In-Depth knowledge and hands-on experience of industry standard and proprietary DFT techniques, such as, SCAN/ATPG, Built-in-Self Test (MBIST/LBIST) Architecture , JTAG (IEEE 1149.x/1500/1687), Boundary Scan (BSCAN) and compression/ decompression technologies on Digital and Mixed Signal SoCs In-Depth knowledge of EDA tools used for DFT, especially Mentor/ Synopsys tools Scripting expertise in Python/PERL, TCL, etc Experience in RTL coding and SDC creation for DFT Modes Recent Tapeout experience in advanced nodes Location - Mumbai, Delhi / NCR, Bengaluru , Kolkata, Chennai, Hyderabad, Ahmedabad, Pune, Remote.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Responsibilities: The role’s day to day responsibilities cover: R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications: BE/BTech/ME/MTech- Computer Science or others Required Skills Develop reliable, scalable, and high-performance Modus DFT software that is easy to use. Develop software tools in C/C++ to support DFT and ATPG. Research and develop software solutions to allow greater efficiency in architecture, hardware, and software teams. Development environment is C++ on Unix in multi-threaded environment with expertise in C++, data-structure and algorithms. Strong knowledge of Tcl is preferred Experience in language compiler Prior experience with large software development projects is highly recommended. We’re doing work that matters. Help us solve what others can’t.

Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI , and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 . Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation , working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Job title Principal Engineer, RTL Design Department Engineering Location Noida Remote No Requisition ID 20019554_2025-03-12

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Responsibilities: The role’s day to day responsibilities cover: R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications: BE/BTech/ME/MTech- Computer Science or others Required Skills Develop reliable, scalable, and high-performance Modus DFT software that is easy to use. Develop software tools in C/C++ to support DFT and ATPG. Research and develop software solutions to allow greater efficiency in architecture, hardware, and software teams. Development environment is C++ on Unix in multi-threaded environment with expertise in C++, data-structure and algorithms. Strong knowledge of Tcl is preferred Experience in language compiler Prior experience with large software development projects is highly recommended. We’re doing work that matters. Help us solve what others can’t.

3 years Service Agreement Experience: 0 - 4 years Role & responsibilities: Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Preferred candidate profile Freshers Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design. Physical Design, Analog Good communication skill. Should be good in Digital Electronics. 3 years Service Agreement.

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications Qualifications: B.Tech with 3+ years or M.Tech with 2+ Years of hands-on experience with end-to-end SD flow - synthesis to GDS using industry standard EDA tool, with a proven track record of successful projects. Has good understanding on timing methodology, constraints building etc. Experience in floorplaning concepts and actual work, and integration of hierarchical design Good understanding and experience with multiple power domains designs. Have hands on experience on LV flow and clean up. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively. Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, initially at the hierarchical level and subsequently at the top-level, reviewing the timing arcs for the .lib generation. Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for DFT. Identify opportunities to optimize clock skew and insertion delay across various corners and modes. Evaluate the clock/reset-domain-crossing (CDC/RDC) issues at the netlisting stage and offer feedback on design fixes or establish waivers if the changes are not feasible. Implement power-saving strategies, such as power gating, multi-voltage domains, and clock gating, to meet low-power objectives while preserving performance standards. Create and refine custom scripts using Tcl, Perl, or Python to enhance workflow efficiency and streamline physical design operations. Mentor and support junior physical design engineers, disseminating best practices and providing technical guidance to elevate team proficiency and performance. PREFERRED EXPERIENCE: Over 8-10+ years of professional experience in constraints generation, synthesis, static timing analysis (STA), and IP-level timing and physical design, with a preference for high-performance SerDes designs. Proven ability in timing analysis, convergence, timing ECOs, and .lib generation. Experience with STA closure on PHYs & understanding the timing requirements across digital and analog macro interfaces is a plus. Proficient in physical design tools such as Synopsys ICC2, Primetime, and the ASIC design flow. Skilled in scripting with Tcl, Python, or Perl to automate and streamline physical design tasks. Excellent problem-solving, leadership, and communication skills and values team culture. Capable of thriving in fast-paced environments and managing multiple projects simultaneously.

We are looking for an adaptive, self-motivative DFT engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The DFT team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development. THE PERSON: You have a passion for modern, digital design, and DFT in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Implementation and verification of DFT features likeSCAN, MBIST, LBIST and JTAG SupportSpyglass-DFTDRC debug and coverage correlation Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Experience in scan-stitching; and has good knowledge of scan-stitching related concepts Exposure to MBIST/BISR implementation and with the Tessent flow of mbist-insertion Excellent hands-on ATPG; and is we'll conversed with the files required to run ATPG Knowledge/experience with Tessent ATPG (mentor) is a plus Knowledge on Spyglass-DFT Excellent hands-on debug skills and scripting skills are critical Knowledge on automation scripts like TCL/AWK/SED is a plus Understands the basics of JTAG Experience with post-silicon bring up is a plus ACADEMIC CREDENTIALS: Bachelors degree w/7+ years or Masters degree w/5+ years in Electronics engineering/Electrical Engineering

Implementation and verification of DFT architecture and features. Scan insertion and ATPG pattern generation. ATPG patterns verification with gate-level simulation. Test coverage and test cost reduction analysis. Post silicon support to ensure successful bring up and enhance yield learning. PREFERRED EXPERIENCE: Understanding of Design for Test methodologies and DFT verification experience (e.g., IEEE1500, JTAG 1149.x, Scan, memory BIST etc.). Experience with Mentor TestKompress and/or Synopsys Tetramax/DFTMAX. Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design.

If you have an experience developing RTL for IP or subsystems and understand architectural specifications, this role is for you. You will be responsible for IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. Key Responsibilities: Design of IP and subsystems with integration of AMD and other 3rd party IPs Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up Lead a subsystem development team of 4 to 5 members. Preferred Experience: 5-7 years full-time experience in IP hardware design Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs Verilog lint tools (Spyglass) and verilog simulation tools (VCS) Clock domain crossing (CDC) tools Detailed understanding of SoC design flows Understanding of IP/SS/SoC Power Management(PM) techniques Power Gating, Clock Gating Experience with embedded processors and data fabric architectures (NoC) Outstanding interaction skills while communicating both written and verbally Ability to work with multi-level functional teams across various geographies Outstanding problem-solving and analytical skills

You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities. KEY RESPONSIBILITIES: Work closely with the SoC Architecture and uArch teams to define the DFT architecture. Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean silicon bring-up Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to comprehend and validate all the usage models Work with the post-silicon team on debug support and to help root-cause any failures Be upto date with the industry trends and bring-in the latest to the AMD products Work with DFT Tool Vendors and drive improvements based on our requirements REQUIREMENTS: 15+ years of in-depth DFT experience having driven multiple Tapeouts and silicon bring-ups across different process nodes. Good understanding and exposure to SoC design and architecture Very good understanding of verif and timing concepts having handled DFT timing closure Exposure to all DFT concepts such as JTAG, SCAN, MBIST, BScan, etc Comfortable with VCS/Verdi and Mentor TK. Logical in thinking and ability to gel we'll within a team Good stakeholder management Ability to quickly adapt to changes and handle pressure Good communication and leadership skills

The ideal candidate for this role should possess a Bachelor's degree or equivalent practical experience along with a minimum of 2 years of experience in developing and maintaining STA constraints and scripts. It is essential to have prior experience working collaboratively in a team of DFT engineers, specifically with Register-Transfer Level (RTL) and Physical Designer Engineers. Preferred qualifications for this position include a Bachelor's or Master's degree in Electrical Engineering or Computer Science, or relevant practical experience. The candidate should have at least 6 years of experience in Static Timing Analysis with exposure to mixed signal design. Proficiency in flow methodology and development is highly desirable, as well as experience in coding using perl, python, and tcl scripting languages. Strong problem-solving and decision-making skills are essential for this role. As part of this role, you will be joining a diverse team dedicated to pushing boundaries and developing custom silicon solutions that drive Google's direct-to-consumer products into the future. Your contributions will be instrumental in shaping the innovation behind products that are beloved by millions globally, with a focus on delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. As a member of our team, you will have the opportunity to leverage the best of Google AI, Software, and Hardware to create revolutionary experiences that are profoundly helpful. Our work involves researching, designing, and developing new technologies and hardware to accelerate computing, ensuring that it is faster, seamless, and more powerful, ultimately aiming to enhance people's lives through innovative technology. Key Responsibilities: - Develop and maintain Static Timing Analysis (STA) and flow methodologies. - Create flow for custom/Analog and Mixed Signal (AMS) IP collateral, encompassing all view generation and QA checks. - Ensure timing closure for Place and Route (PnR) blocks. - Validate time constraint development. In this role, your expertise and contributions will play a crucial role in advancing the next generation of hardware experiences, contributing to a future where technology enhances and enriches the lives of individuals worldwide.,